CyberResearch
®
CPU Cards
CZGL AT-16
CyberResearch, Inc
.
177
25 Business Park Drive
P: (203) 643-5000; F: (203) 643-5001
Branford, CT USA
www.cyberresearch.com
C.1 Introduction
The DIO connector on the CZGL AT-16 is interfaced to GPIO ports on the Super I/O
chipset. The DIO has both 4-bit digital inputs and 4-bit digital outputs. The digital inputs
and digital outputs are generally control signals that control the on/off circuit of external
devices or TTL devices. Data can be read or written to the selected address to enable the
DIO functions.
NOTE:
For further information, please refer to the datasheet for the Super I/O
chipset.
C.2 DIO Connector Pinouts
The following table describes how the DIO connector pins are connected to the Digital I/O
port.
Pin Description Super
I/O
Pin Super
I/O
Pin
Description
1 Ground
N/A
N/A
2 VCC
N/A
N/A
3
Output 3
24
General Purpose I/O 23
4
Output 2
25
General Purpose I/O 22
5
Output 1
26
General Purpose I/O 21
6
Output 0
27
General Purpose I/O 20
7
Input 3
16
General Purpose I/O 33
8
Input 2
17
General Purpose I/O 32
9
Input 1
18
General Purpose I/O 31
10
Input 0
19
General Purpose I/O 30
Table C-1: Digital I/O Connector Pinouts
Summary of Contents for CZGL AT-16
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