CyberResearch
®
CPU Cards
CZGL AT-16
CyberResearch, Inc
.
23
25 Business Park Drive
P: (203) 643-5000; F: (203) 643-5001
Branford, CT USA
www.cyberresearch.com
Integrated 10/100/1000 transceiver
Auto-Negotiation with Next Page capability
Supports PCI Express™ 1.1
Supports pair swap/polarity/skew correction
Crossover Detection & & Auto-Correction
Wake-on-LAN and remote wake-up support
Microsoft® NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send and Giant send) support
Supports Full Duplex flow control (IEEE 802.3x)
Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supports IEEE 802.1P Layer 2 Priority Encoding
Supports IEEE 802.1Q VLAN tagging
Serial
EEPROM
Transmit/Receive on-chip buffer support
Supports power down/link down power saving
Supports PCI MSI (Message Signaled Interrupt) and MSI-X
Supports Receive-Side Scaling (RSS)
2.5.9 SPI Bus Components
The Intel® ICH7M SPI bus is connected to components listed below:
BIOS
chip
2.5.9.1 SPI BIOS
The 4-pin Serial Peripheral Interface (SPI) is connected to an SPI BIOS chip. A licensed
copy of AMI BIOS is preinstalled on the SPI BIOS chip. A master-slave protocol is used for
communication on the SPI bus. The slave is connected to the Intel® ICH7M and is
implemented as a tri-state bus. The SPI BIOS is located on the reverse side of the JSPI1
jumper.
Summary of Contents for CZGL AT-16
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