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CY62148E MoBL

®

Document #: 38-05442 Rev. *F

Page 4 of 10

Thermal Resistance 

[10]

Parameter

Description

Test Conditions

SOIC

Package

TSOP II

Package

Unit

Θ

JA

Thermal Resistance 

(Junction to Ambient)

Still Air, soldered on a 3 × 4.5 inch, 

two-layer printed circuit board

75

77

°

C/W

Θ

JC

Thermal Resistance 

(Junction to Case)

10

13

°

C/W

AC Test Loads and Waveforms

Parameters

5.0V

Unit

R1

1800

R2

990

R

TH

639

V

TH

1.77

V

Data Retention Characteristics

 (Over the Operating Range)

Parameter

Description

Conditions

Min

Typ 

[3]

Max Unit

V

DR

V

CC

 for Data Retention

2

V

I

CCDR

Data Retention Current

V

CC

= V

DR

, CE > V

CC

 – 0.2V, 

V

IN

 > V

CC

 – 0.2V or V

IN

 < 0.2V

Ind’l/Auto-A

1

7

µ

A

t

CDR 

[10]

Chip Deselect to Data Retention Time

0

ns

t

[11]

Operation Recovery Time

t

RC

ns

Data Retention Waveform

3.0V

V

CC

OUTPUT

R2

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

Rise Time = 1 V/ns

Fall Time = 1 V/ns

OUTPUT

V

Equivalent to:

THEVENIN

EQUIVALENT

ALL INPUT PULSES

R

TH

R1

V

CC(min)

V

CC(min)

t

CDR

V

DR

> 2.0V

DATA RETENTION MODE

t

R

V

CC

CE

Note

11. Full device operation requires linear V

CC

 ramp from V

DR 

to V

CC(min)

 > 100 

µ

s or stable at V

CC(min)

 > 100 

µ

s.

[+] Feedback 

Summary of Contents for CY62148E

Page 1: ...educes power consumption by more than 99 when deselected CE HIGH The eight input and output pins IO0 through IO7 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH Write operation is active CE LOW and WE LOW To write to the device take Chip Enable CE and Write Enable WE inputs LOW Data on the eight IO pins IO0 through IO7 is then written into the location spe...

Page 2: ...A 13 A 14 A 15 A 16 A 17 ROW DECODER COLUMN DECODER 512K x 8 ARRAY INPUT BUFFER A10 A11 A12 A 18 Note 4 NC pins are not connected on the die 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 32 pin SOIC TSOP II Pinout Top View A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 VSS VCC A18 WE OE CE Feedback ...

Page 3: ...8 V For SOIC package 0 5 0 6 8 IIX Input Leakage Current GND VI VCC 1 1 1 1 µA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 1 1 µA ICC VCC Operating Supply Current f fmax 1 tRC VCC VCC max IOUT 0 mA CMOS levels 15 20 15 20 mA f 1 MHz 2 2 5 2 2 5 ISB2 9 AutomaticCEPower down Current CMOS Inputs CE VCC 0 2V VIN VCC 0 2V or VIN 0 2V f 0 VCC VCC max 1 7 1 7 µA Capacitance For All Packages...

Page 4: ...perating Range Parameter Description Conditions Min Typ 3 Max Unit VDR VCC for Data Retention 2 V ICCDR Data Retention Current VCC VDR CE VCC 0 2V VIN VCC 0 2V or VIN 0 2V Ind l Auto A 1 7 µA tCDR 10 Chip Deselect to Data Retention Time 0 ns tR 11 Operation Recovery Time tRC ns Data Retention Waveform 3 0V VCC OUTPUT R2 30 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 Rise Time 1 V ns Fall Time 1 V n...

Page 5: ...s tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High Z 13 14 18 20 ns tLZWE WE HIGH to Low Z 13 10 10 ns Notes 12 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3V and output loading of the specified IOL IOH as shown in the AC Test ...

Page 6: ...MPEDANCE tHZOE tHZCE tPD IMPEDANCE ICC ISB HIGH ADDRESS CE DATA OUT VCC SUPPLY CURRENT OE DATA VALID tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE ADDRESS CE WE DATA IO OE NOTE 21 Notes 16 Device is continuously selected OE CE VIL 17 WE is HIGH for read cycles 18 Address valid before or similar to CE transition LOW 19 Data IO is high impedance if OE VIH 20 If CE goes HIGH simultaneously with WE HIGH the...

Page 7: ...de Power H X X High Z Deselect Power down Standby ISB L H L Data Out Read Active ICC L L X Data In Write Active ICC L H H High Z Selected Outputs Disabled Active ICC Switching Waveforms continued tWC DATA VALID tAW tSA tPWE tHA tHD tSD tSCE ADDRESS CE DATA IO WE DATA VALID tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE ADDRESS CE WE DATA IO NOTE 21 Feedback ...

Page 8: ...n Thin Small Outline Package II Pb free Industrial 55 CY62148ELL 55SXI 51 85081 32 pin Small Outline Integrated Circuit Pb free Industrial 55 CY62148ELL 55SXA 51 85081 32 pin Small Outline Integrated Circuit Pb free Automotive A Contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 1 32 pin TSOP II 51 85095 51 85095 Feedback ...

Page 9: ...t systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Figure 2 32 pin 450 MIL Molded SOIC 51 85081 MoBL is a registered trademark and More Battery Life is a ...

Page 10: ...ion Court Removed 35ns Speed Bin Removed L version of CY62148E Changed ICC Typ value from 1 5 mA to 2 mA at f 1 MHz Changed ICC Max value from 2 mA to 2 5 mA at f 1 MHz Changed ICC Typ value from 12 mA to 15 mA at f fmax Removed ISB1 spec from the Electrical characteristics table Changed ISB2 Typ values from 0 7 µA to 1 µA and Max values from 2 5 µA to 7 µA Modified footnote 4 to include current l...

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