Cypress Semiconductor CY7C1012DV33 Specification Sheet Download

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CY7C1012DV33

Document Number: 38-05610 Rev. *D

Page 10 of 11

Document History Page

Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM
Document Number: 38-05610

Rev.

ECN No.

Orig. of

Change

Submission

Date

Description of Change

250650

SYT

See ECN

New data sheet

469517

NXR

See ECN

Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed –10 and –12 speed bins from product offering
Changed J7 Ball of BGA from DNU to NC
Removed Industrial Operating range from product offering
Included the Maximum ratings for Static Discharge Voltage and Latch Up Current
on page 3
Changed I

CC(Max)

from 220 mA to 150 mA

Changed I

SB1(Max)

from 70 mA to 30 mA

Changed I

SB2(Max)

from 40 mA to 25 mA

Specified the Overshoot specification in footnote 1
Updated the Truth Table
Updated the Ordering Information table

499604

NXR

See ECN

Added note 1 for NC pins
Changed I

specification from 150 mA to 185 mA

Updated Test Condition for I

in DC Electrical Characteristics table

Added note for t

ACE

, t

LZCE

, t

HZCE

, t

, and t

SCE

in AC Switching Characteristics

Table on page 4

1462585

VKN

See ECN

Converted from preliminary to final
Updated block diagram
Changed I

specification from 185 mA to 225 mA

Updated thermal specs

2604677

VKN/PYRS

11/12/08

Removed Commercial operating range, Added Industrial operating range
Removed 8 ns speed bin, Added 10 ns speed bin,
Modified footnote# 3

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Summary of Contents for CY7C1012DV33

Page 1: ...en the chip select controlling that byte is LOW and the write enable input WE input is LOW Data on the respective input and output I O pins is then written into the location specified on the address pins A0 A18 Asserting all of the chip selects LOW and write enable LOW writes all 24 bits of data into the SRAM Output enable OE is ignored while in WRITE mode Data bytes are also individually read fro...

Page 2: ... NC CE2 NC CE3 NC I O0 D I O13 VDD VSS VSS VSS VDD I O1 E I O14 VSS VDD VSS VDD VSS I O2 F I O15 VDD VSS VSS VSS VDD I O3 G I O16 VSS VDD VSS VDD VSS I O4 H I O17 VDD VSS VSS VSS VDD I O5 J NC VSS VDD VSS VDD VSS NC K I O18 VDD VSS VSS VSS VDD I O6 L I O19 VSS VDD VSS VDD VSS I O7 M I O20 VDD VSS VSS VSS VDD I O8 N I O21 VSS VDD VSS VDD VSS I O9 P I O22 VDD VSS VSS VSS VDD I O10 R I O23 A NC NC NC...

Page 3: ...Parameter Description Test Conditions 3 10 Unit Min Max VOH Output HIGH Voltage VCC Min IOH 4 0 mA 2 4 V VOL Output LOW Voltage VCC Min IOL 8 0 mA 0 4 V VIH Input HIGH Voltage 2 0 VCC 0 3 V VIL 2 Input LOW Voltage 0 3 0 8 V IIX Input Leakage Current GND VI VCC 1 1 μA IOZ Output Leakage Current GND VOUT VCC output disabled 1 1 μA ICC VCC Operating Supply Current VCC Max f fMAX 1 tRC IOUT 0 mA CMOS ...

Page 4: ... to ambient Still air soldered on a 3 4 5 inch four layer printed circuit board 20 31 C W ΘJC Thermal Resistance junction to case 8 35 C W Figure 2 AC Test Loads and Waveforms 4 90 10 3 0V GND 90 10 All input pulses 3 3V OUTPUT 5 pF a b R1 317 Ω R2 351Ω Fall Time 1V ns c OUTPUT 50Ω Z0 50Ω VTH 1 5V 30 pF Capacitive Load consists of all components of the test environment Rise Time 1V ns Including ji...

Page 5: ...o Low Z 7 3 ns tHZWE WE LOW to High Z 7 5 ns Notes 5 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V and input pulse levels of 0 to 3 0V Test conditions for the read cycle use output loading as shown in part a of Figure 2 unless specified otherwise 6 tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first ...

Page 6: ...re 4 Read Cycle No 2 OE Controlled 3 14 15 3 0V 3 0V tCDR VDR 2V DATA RETENTION MODE tR CE VCC PREVIOUS DATA VALID DATA VALID RC tAA tOHA tRC ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tPD tHZCE OE CE ADDRESS DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE ICC ISB Notes 11 Tested initially and after any design or process changes that may affect these parameters...

Page 7: ...ALID tAW tSA tPWE tHA tHD tSD tSCE tSCE CE WE DATA I O ADDRESS tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE DATAIN VALID CE ADDRESS WE DATA I O OE NOTE 18 DATA VALID tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE CE ADDRESS WE DATA I O NOTE 18 Notes 16 Data I O is high impedance if OE VIH 17 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state 18 During this per...

Page 8: ...High Z Data Out High Z Read Active ICC H H L L H High Z High Z Data Out Read Active ICC L L L L H Full Data Out Full Data Out Full Data Out Read Active ICC L H H X L Data In High Z High Z Write Active ICC H L H X L High Z Data In High Z Write Active ICC H H L X L High Z High Z Data In Write Active ICC L L L X L Full Data In Full Data In Full Data In Write Active ICC L L L H H High Z High Z High Z ...

Page 9: ...dering Information Speed ns Ordering Code Package Name Package Type Operating Range 10 CY7C1012DV33 10BGXI 51 85115 119 Ball Plastic Ball Grid Array 14 x 22 x 2 4 mm Pb Free Industrial Package Diagram Figure 8 119 Ball PBGA 14 x 22 x 2 4 mm 51 85115 B Feedback ...

Page 10: ...hanged ICC Max from 220 mA to 150 mA Changed ISB1 Max from 70 mA to 30 mA Changed ISB2 Max from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Updated the Truth Table Updated the Ordering Information table B 499604 NXR See ECN Added note 1 for NC pins Changed ICC specification from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note...

Page 11: ...n of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials ...

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