CY7C1012DV33
Document Number: 38-05610 Rev. *D
Page 5 of 11
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Description
–10
Unit
Min
Max
Read Cycle
t
power
[6]
V
CC
(Typical) to the First Access
100
μ
s
t
RC
Read Cycle Time
10
ns
t
AA
Address to Data Valid
10
ns
t
OHA
Data Hold from Address Change
3
ns
t
ACE
CE
Active LOW to Data Valid
[3]
10
ns
t
DOE
OE LOW to Data Valid
5
ns
t
LZOE
OE LOW to Low Z
[7]
1
ns
t
HZOE
OE HIGH to High Z
[7]
5
ns
t
LZCE
CE
Active LOW to Low Z
[3, 7]
3
ns
t
HZCE
CE Deselect
HIGH to High Z
[3, 7]
5
ns
t
PU
CE
Active LOW to Power Up
[3, 8]
0
ns
t
PD
CE Deselect
HIGH to Power Down
[3, 8]
10
ns
Write Cycle
[9, 10]
t
WC
Write Cycle Time
10
ns
t
SCE
CE
Active LOW to Write End
[3]
7
ns
t
AW
Address Setup to Write End
7
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
7
ns
t
SD
Data Setup to Write End
5.5
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
ns
t
HZWE
WE LOW to High Z
[7]
5
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of
Figure 2
, unless specified otherwise.
6. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
7. t
HZOE
, t
HZCE
, t
HZWE
, t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in part (b) of
Figure 2
. Transition is measured
±
200 mV from steady state
voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE
1
or CE
2
or CE
3
LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate
a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
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