Cypress Semiconductor CY8C24223A Specification Sheet Download

Page: 20 / 31

CY8C24223A, CY8C24423A

Document Number: 3-12029 Rev. *E

Page 20 of 31

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40

≤

125

C. Typical parameters apply to 5V at 25

C and are for design guidance only.

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40

≤

125

C. Typical parameters apply to 5V at 25

C and are for design guidance only.

Note

The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the

PSoC Programmable

System-on-Chip Technical Reference Manual

for more information on the VLT_CR register.

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40

≤

125

C. Typical parameters apply to 5V at 25

C and are for design guidance only.

Table 17. DC Analog PSoC Block Specifications

Symbol

Description

Min

Typ

Max

Units

Resistor Unit Value (Continuous Time)

–

12.24

–

Capacitor Unit Value (Switch Cap)

–

Table 18. DC POR and LVD Specifications

Symbol

Description

Min

Typ

Max

Units

PPOR2R

Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 10b

4.55

4.70

PPOR2

Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 10b

4.55

PH2

PPOR Hysteresis
PORLEV[1:0] = 10b

–

LVD6

LVD7

Vdd Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b

4.62

4.710

4.73

4.814

4.83

4.950

V
V

Table 19. DC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Vdd

IWRITE

Supply Voltage for Flash Write Operations

4.75

–

DDP

Supply Current During Programming or Verify

–

ILP

Input Low Voltage During Programming or Verify

–

0.8

IHP

Input High Voltage During Programming or Verify

2.2

–

ILP

Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify

–

0.2

Driving internal
pull down resistor.

IHP

Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify

–

1.5

Driving internal
pull down resistor.

OLV

Output Low Voltage During Programming or Verify

–

Vss + 0.75

OHV

Output High Voltage During Programming or Verify

3.5

–

Vdd

Flash

ENPB

Flash Endurance (per block)

a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writ-

ing. Refer to the Flash APIs Application Note

AN2015

http://www.cypress.com

under Application Notes for more information.

100

–

Erase/write
cycles per block.

Flash

ENT

Flash Endurance (total)

a,b

b. A maximum of 64 x 100 block endurance cycles is allowed.

6,400

–

Erase/write
cycles.

Flash

Flash Data Retention

Flash data retention based on the use condition of

≤

7000 hours at T

≤

125°C and the remaining time at T

≤

65°C.

–

Years

[+] Feedback

Summary of Contents for CY8C24223A

Page 1: ...se Write Cycles 256 Bytes SRAM Data Storage In System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes Programmable Pin Configurations 25 mA Sink on All GPIO Pull Up Pull Down High Z Strong or Open Drain Drive Modes on All GPIO Up to Ten Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on All GPIO Additional System Resources I2 C Slave Master and...

Page 2: ...z ILO internal low speed oscillator is provided for the Sleep timer and WDT If crystal accuracy is desired the ECO 32 768 kHz external crystal oscillator is available for use as a Real Time Clock RTC and can optionally generate a crystal accurate 24 MHz system clock using a PLL The clocks together with programmable clock dividers as a System Resource provide the flexibility to integrate almost any...

Page 3: ...lectable gain to 93x Comparators up to two with 16 selectable thresholds DACs up to two with 6 to 9 bit resolution Multiplying DACs up to two with 6 to 9 bit resolution High current output drivers two with 30 mA drive as a PSoC Core resource 1 3V reference as a System Resource DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible Analog blocks are arranged in a column of...

Page 4: ...ing and Electrical Specification information refer the latest PSoC device data sheets on the web at http www cypress com psoc Development Kits Development Kits are available from the following distributors Digi Key Avnet Arrow and Future The Cypress Online Store contains development kits C compilers and all accessories for PSoC development Go to the Cypress Online Store web site at http www cypres...

Page 5: ...et for a given project configuration for use during application programming in conjunction with the Device Data Sheet After the framework is generated the user can add application specific code to flesh out the framework It is also possible to change the selected components and regenerate the framework Design Browser The Design Browser allows users to select and import preconfigured designs into t...

Page 6: ...e peripheral functions called User Modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties The standard User Module library contains over 50 common peripherals such as ADCs DACs Timers Counters UARTs and other not so common peripherals such as DTMF Generators and Bi Quad analog filter sections Each user module establishes...

Page 7: ... allows you define complex breakpoint events that include monitoring address and data bus values memory locations and external signals Document Conventions Acronyms Used The following table lists the acronyms that are used in this document Units of Measure A units of measure table is located in the Electrical Specifications section Table 5 on page 10 lists all the abbreviations used to measure the...

Page 8: ...l Data SDA 8 IO P1 3 9 IO P1 1 Crystal Input XTALin I2C Serial Clock SCL ISSP SCLK 10 Power Vss Ground connection 11 IO P1 0 Crystal Output XTALout I2C Serial Data SDA ISSP SDATA 12 IO P1 2 13 IO P1 4 Optional External Clock Input EXTCLK 14 IO P1 6 15 Input XRES Active high external reset with internal pull down 16 IO I P0 0 Analog column mux input 17 IO I P0 2 Analog column mux input 18 IO I P0 4...

Page 9: ...l External Clock Input EXTCLK 18 IO P1 6 19 Input XRES Active high external reset with internal pull down 20 IO I P2 0 Direct switched capacitor block input 21 IO I P2 2 Direct switched capacitor block input 22 IO P2 4 External Analog Ground AGND 23 IO P2 6 External Voltage Reference VRef 24 IO I P0 0 Analog column mux input 25 IO I P0 2 Analog column mux input 26 IO I P0 4 Analog column mux input...

Page 10: ...able Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is referred to as IO space and is divided into two banks The XOI bit in the Flag register CPU_F determines which bank the user is currently in When the XOI bit is set the user is in Bank 1 Note In the following register mapping tables blank fields are Reserved and must not be accessed Ta...

Page 11: ...2 13 53 ASD20CR3 93 RW D3 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW I2C_CFG D6 RW 17 57 ASC21CR3 97 RW I2C_SCR D7 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF DBB00DR0 20 AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 ...

Page 12: ...t not be accessed Access is bit specific Table 7 Register Map Bank 1 Table Configuration Space Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access PRT0DM0 00 RW 40 ASC10CR0 80 RW C0 PRT0DM1 01 RW 41 ASC10CR1 81 RW C1 PRT0IC0 02 RW 42 ASC10CR2 82 RW C2 PRT0IC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT...

Page 13: ...W DCB02OU 2A RW 6A AA BDG_TR EA RW 2B 6B AB ECO_TR EB W DCB03FN 2C RW 6C AC EC DCB03IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE 2F 6F AF EF 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7...

Page 14: ...ction Table 8 Units of Measure Symbol Unit of Measure Symbol Unit of Measure oC degree Celsius μW microwatts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kΩ kilohm W ohm MHz megahertz pA picoampere MΩ megaohm pF picofarad μA microampere pp peak to peak μF microfarad ppm parts p...

Page 15: ...Temperature with Power Applied 40 125 o C Vdd Supply Voltage on Vdd Relative to Vss 0 5 5 75 V VIO DC Input Voltage Vss 0 5 Vdd 0 5 V VIOZ DC Voltage Applied to Tri state Vss 0 5 Vdd 0 5 V IMIO Maximum Current into any Port Pin 25 25 mA ESD Electro Static Discharge Voltage 2000 V Human Body Model ESD LU Latch up Current 200 mA Table 10 Operating Temperature Symbol Description Min Typ Max Units Not...

Page 16: ...er and WDT at high temperature a 4 100 μA Conditions are with internal slow speed oscillator Vdd 5 25V 55 oC TA 125 o C Analog power off ISBXTL Sleep Mode Current with POR LVD Sleep Timer WDT and external crystal a 6 15 μA Conditions are with properly loaded 1 μW max 32 768 kHz crystal Vdd 5 25V 40 oC TA 55 oC Analog power off ISBXTLH Sleep Mode Current with POR LVD Sleep Timer WDT and external cr...

Page 17: ...Input Capacitance Port 0 Analog Pins 4 5 10 pF Package and pin dependent Temp 25o C VCMOA Common Mode Voltage Range Common Mode Voltage Range high power or high opamp bias 0 0 Vdd Vdd 0 5 V The common mode input voltage range is measured through an analog output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer 0 5 GOLOA Open Loop Gain Pow...

Page 18: ...nly Table 14 DC Low Power Comparator Specifications Symbol Description Min Typ Max Units VREFLPC Low power comparator LPC reference voltage range 0 2 Vdd 1 V ISLPC LPC supply current 10 40 μA VOSLPC LPC voltage offset 2 5 30 mV Table 15 DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units VOSOB Input Offset Voltage Absolute Value 3 18 mV TCVOSOB Input Offset Voltage Drift 6 ...

Page 19: ...e local buffer in the PSoC block Bandgap voltage is 1 3V 0 05V Vdd 2 0 02 Vdd 2 Vdd 2 0 02 V AGND 2 x BandGapa CT Block Power High 2 4 2 6 2 8 V AGND P2 4 P2 4 Vdd 2 a CT Block Power High P2 4 0 02 P2 4 P2 4 0 02 V AGND BandGapa CT Block Power High 1 23 1 30 1 37 V AGND 1 6 x BandGapa CT Block Power High 1 98 2 08 2 14 V AGND Column to Column Variation AGND Vdd 2 a CT Block Power High 0 035 0 000 ...

Page 20: ...70 V VPPOR2 Vdd Value for PPOR Trip negative ramp PORLEV 1 0 10b 4 55 V VPH2 PPOR Hysteresis PORLEV 1 0 10b 0 mV VLVD6 VLVD7 Vdd Value for LVD Trip VM 2 0 110b VM 2 0 111b 4 62 4 710 4 73 4 814 4 83 4 950 V V Table 19 DC Programming Specifications Symbol Description Min Typ Max Units Notes VddIWRITE Supply Voltage for Flash Write Operations 4 75 V IDDP Supply Current During Programming or Verify 1...

Page 21: ...for information on maximum frequencies for user modules MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F32K2 External Crystal Oscillator 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle FPLL PLL Frequency 23 986 MHz A multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL 800 ps TPLLSLEW PLL Lock Time 0 5 10 ms TPLLSLEWSLOW PLL Lock Time for Low ...

Page 22: ...ng Timing Diagram Figure 10 External Crystal Oscillator Startup Timing Diagram Figure 11 24 MHz Period Jitter IMO Timing Diagram Figure 12 32 kHz Period Jitter ECO Timing Diagram 24 MHz FPLL PLL Enable TPLLSLEW PLL Gain 0 24 MHz FPLL PLL Enable TPLLSLEWLOW PLL Gain 1 32 kHz F32K2 32K Select TOS Jitter24M1 F24M Jitter32k F32K2 Feedback ...

Page 23: ...load 50 pF 2 22 ns Vdd 4 75 to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 2 22 ns Vdd 4 75 to 5 25V 10 90 TRiseS Rise Time Slow Strong Mode Cload 50 pF 9 27 ns Vdd 4 75 to 5 25V 10 90 TFallS Fall Time Slow Strong Mode Cload 50 pF 9 22 ns Vdd 4 75 to 5 25V 10 90 TFallF TFallS TRiseF TRiseS 90 10 GPIO Pin Output Voltage Table 22 AC Operational Amplifier Specifications Symbol Descrip...

Page 24: ... the corner frequency defined by the on chip 8 1k resistance and the external capacitor Figure 14 Typical AGND Noise with P2 4 Bypass At low frequencies the opamp noise is proportional to 1 f power independent and determined by device geometry At high frequencies increased power level reduces the noise spectrum level Figure 15 Typical Opamp Noise Table 23 AC Low Power Comparator Specifications Sym...

Page 25: ... Frequency With Capture 24 96 MHz Counter Enable Pulse Width 50a ns Maximum Frequency No Enable Input 24 96 MHz 4 75V Vdd 5 25V Maximum Frequency Enable Input 24 96 MHz Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 50a ns Disable Mode 50a ns Maximum Frequency 24 96 MHz 4 75V Vdd 5 25V CRCPRS PRS Mode Maximum Input Clock Frequency 24 96 MHz 4 75V Vdd 5 25V CRCP...

Page 26: ...Settling Time to 0 1 1V Step 100 pF Load Power Low Power High 3 3 μs μs TSOB Falling Settling Time to 0 1 1V Step 100 pF Load Power Low Power High 3 3 μs μs SRROB Rising Slew Rate 20 to 80 1V Step 100 pF Load Power Low Power High 0 6 0 6 V μs V μs SRFOB Falling Slew Rate 80 to 20 1V Step 100 pF Load Power Low Power High 0 6 0 6 V μs V μs BWOB Small Signal Bandwidth 20mVpp 3dB BW 100 pF Load Power ...

Page 27: ... of the SCL Clock 4 0 0 6 μs TSUSTAI2C Setup Time for a Repeated START Condition 4 7 0 6 μs THDDATI2C Data Hold Time 0 0 μs TSUDATI2C Data Setup Time 250 100a a A Fast Mode I2C bus device can be used in a Standard Mode I2C bus system but the requirement tSU DAT 250 ns must then be met This is automatically the case if the device does not stretch the LOW period of the SCL signal If such device does...

Page 28: ...e thermal impedances for each package and the typical package capacitance on crystal pins Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tools dimensions refer to the document titled PSoC Emulator Pod Dimensions at http www cypress com design MR10161 Figure 17 20 Pin 210 Mil SSOP 51 85077 C Feedback ...

Page 29: ...e Typical θJA 20 SSOP 117 o C W 28 SSOP 101 o C W TJ TA POWER x θJA Table 30 Typical Package Capacitance on Crystal Pins Package Package Capacitance 20 SSOP 2 6 pF 28 SSOP 2 8 pF Table 31 Solder Reflow Peak Temperature Package Minimum Peak Temperature Maximum Peak Temperature 20 SSOP 240o C 260o C 28 SSOP 240oC 260oC Higher temperatures may be required based on the solder melting point Typical tem...

Page 30: ... Blocks Digital IO Pins Analog Inputs Analog Outputs XRES Pin 20 Pin 210 Mil SSOP CY8C24223A 12PVXE 4K 256 No 40 C to 125 C 4 6 16 8 2 Yes 20 Pin 210 Mil SSOP Tape and Reel CY8C24223A 12PVXET 4K 256 No 40 C to 125 C 4 6 16 8 2 Yes 28 Pin 210 Mil SSOP CY8C24423A 12PVXE 4K 256 No 40 C to 125 C 4 6 24 10 2 Yes 28 Pin 210 Mil SSOP Tape and Reel CY8C24423A 12PVXET 4K 256 No 40 C to 125 C 4 6 24 10 2 Ye...

Page 31: ...ess written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the appl...

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