Cypress Semiconductor FLEx18 CY7C0830AV, Specification Sheet

Page 1: ... one port at the same time is undefined Registers on control address and data lines allow for minimal setup and hold time During a Read operation data is registered for decreased cycle time Each port contains a burst counter on the input address register After externally loading the counter with the initial address the counter increments the address internally more details to follow The internal W...

Page 2: ...ic JTAG TDO TMS TCK TDI MRST DQ9L DQ17L DQ0L DQ8L I O Control 9 9 CE0L CE1L R WL B0L B1L OEL A0R A18R CLKR ADS CNTEN CNTRSTR 19 Addr Read Back CNTINTR Mask Register Counter Address Register CNT MSKR Address Decode Interrupt Logic INTR I O Control 9 9 CE0R CE1R R WR B0R B1R OER Mirror Reg Mirror Reg DQ0R DQ8R DQ9R DQ17R Note 2 CY7C0837AV has 15 address bits CY7C0830AV has 16 address bits CY7C0831AV...

Page 3: ...R H A12L A13L OEL NC VDD VSS VSS VDD NC OER A13R A12R J A14L A15L 3 RWL NC VDD VDD VDD VDD NC RWR A15R 3 A14R K A16L 4 A17L 5 CNT MSKL 7 TDO CNTRSTL 7 TCK TMS CNTRSTR 7 TDI CNT MSKR 7 A17R 5 A16R 4 L A18L 6 NC DQ6L DQ4L DQ2L CNTENL 8 CNTENR 8 DQ2R DQ4R DQ6R NC A18R 6 M DQ8L DQ7L DQ5L DQ3L DQ1L DQ0L DQ0R DQ1R DQ3R DQ5R DQ7R DQ8R Notes 3 Leave this ball unconnected for CY7C0837AV 4 Leave this ball u...

Page 4: ...69 68 67 66 65 64 63 62 61 B1R VSS VDD CE0R OER B0R CE1R A7R A6R A5R A4R VDD VSS A3R A2R A12R A13R VDD VSS A11R A10R A9R A8R CNT MSKR CNTRSTR CNTENR ADSR MRST CLKR R WR 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 V SS DQ 0L DQ 1L DQ 2L DQ 3L V DD DQ 4L DQ 5L DQ 6L DQ 7L DQ 8L A 17L 10 A 16L 9 A 15L A 14L A 17R 10 A 14R A 15R A 16R 9 DQ 8R DQ 7R DQ 6R D...

Page 5: ...must be asserted LOW to enable the DQ data pins during Read operations INTL INTR Mailbox Interrupt Flag Output The mailbox permits communications between ports The upper two memory locations are used for message passing INTL is asserted LOW when the right port writes to the mailbox location of the left port and vice versa An interrupt to a port is deasserted HIGH when it reads the contents of its ...

Page 6: ...counter register into two regions zero or more 0s in the most significant bits define the masked region one or more 1s in the least significant bits define the unmasked region Bit 0 may also be 0 masking the least significant counter bit and causing the counter to increment by two instead of one The mirror register is used to reload the counter register on increment operations see Retransmit on pa...

Page 7: ... address starts at address 8h The counter increments its internal address value until it reaches the mask register value of 3Fh The counter wraps around the memory block to location 8h at the next count CNTINT is issued when the counter reaches its maximum value Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles Su...

Page 8: ...he mask register to all 1s Mask Load Operation The mask register is loaded with the address value presented at the address lines Not all values permit correct increment opera tions Permitted values are of the form 2n 1 or 2n 2 From the most significant bit to the least significant bit permitted values have zero or more 0s one or more 1s or one 0 Thus 3FFFF 003FE and 00001 are permitted values but ...

Page 9: ...m Mask Register Mirror Counter Address Decode RAM Array Wrap 1 0 Increment Logic 1 0 1 2 1 0 Wrap Detect From Mask From Counter To Counter Bit 0 Wrap 17 17 17 17 17 1 0 Load Increment CNT MSK CNTEN ADS CNTRST CLK Decode Logic Bidirectional Address Lines Mask Register Counter Address Register From Address Lines To Readback and Address Decode 17 17 MRST Feedback ...

Page 10: ...o form the scan chain of the CY7C0833AV as shown in Figure 5 on page 11 TMS and TCK are connected in parallel to each DIE to drive all TAP controllers in unison In many cases each DIE is supplied with the same instruction In other cases it might be useful to supply different instructions to each DIE One example would be testing the device ID of one DIE while bypassing the others Each pin of FLEx18...

Page 11: ... Register Name Bit Size Instruction 4 Bypass 1 Identification 32 Boundary Scan n 22 Table 6 Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input Output ring contents Places the BSR between the TDI and TDO BYPASS 1111 Places the BYR between TDI and TDO IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO HIGHZ 0111 Pla...

Page 12: ...ent Except TDI TMS MRST 10 10 10 10 10 10 μA IIX2 Input Leakage Current TDI TMS MRST 0 1 1 0 0 1 1 0 0 1 1 0 mA ICC Operating Current for VDD Max IOUT 0 mA Outputs Disabled CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0832BV 225 300 225 300 mA CY7C0833AV 270 400 200 310 mA ISB1 25 Standby Current Both Ports TTL Level CEL and CER VIH f fMAX 90 115 90 115 90 115 mA ISB2 25 Standby Current One Por...

Page 13: ... tHA Address Hold Time 0 6 0 6 0 6 0 6 ns tSB Byte Select Setup Time 2 3 2 5 2 5 3 0 ns tHB Byte Select Hold Time 0 6 0 6 0 6 0 6 ns tSC Chip Enable Setup Time 2 3 2 5 NA NA ns tHC Chip Enable Hold Time 0 6 0 6 NA NA ns tSW R W Setup Time 2 3 2 5 2 5 3 0 ns tHW R W Hold Time 0 6 0 6 0 6 0 6 ns tSD Input Data Setup Time 2 3 2 5 2 5 3 0 ns tHD Input Data Hold Time 0 6 0 6 0 6 0 6 ns tSAD ADS Setup T...

Page 14: ...t Time 0 5 6 7 0 5 7 5 0 5 7 5 0 5 10 ns tSCINT Clock to CNTINT Set Time 0 5 5 0 0 5 5 7 NA NA NA NA ns tRCINT Clock to CNTINT Reset time 0 5 5 0 0 5 5 7 NA NA NA NA ns Port to Port Delays tCCS Clock to Clock Skew 5 2 6 0 6 0 8 0 ns Master Reset Timing tRS Master Reset Pulse Width 7 0 7 5 7 5 10 ns tRS Master Reset Setup Time 6 0 6 0 6 0 8 5 ns tRSR Master Reset Recovery Time 6 0 7 5 7 5 10 ns tRS...

Page 15: ...CYC TCK Clock Cycle Time 100 ns tTH TCK Clock HIGH Time 40 ns tTL TCK Clock LOW Time 40 ns tTMSS TMS Setup to TCK Clock Rise 10 ns tTMSH TMS Hold After TCK Clock Rise 10 ns tTDIS TDI Setup to TCK Clock Rise 10 ns tTDIH TDI Hold After TCK Clock Rise 10 ns tTDOV TCK Clock LOW to TDO Valid 30 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Figure 7 JTAG Switching Waveform Test Clock Test Mode Select TCK T...

Page 16: ...ATAOUT OE An 2 An 3 tSC tHC tOHZ tOE tOLZ tDC tCD2 tCKLZ Qn Qn 1 Qn 2 1 Latency BE0 BE1 tSB tHB Notes 30 OE is asynchronously controlled all other inputs excluding MRST and JTAG are synchronous to the rising clock edge 31 ADS CNTEN LOW and MRST CNTRST CNT MSK HIGH 32 The output is disabled high impedance state by CE VIH following the next rising edge of the clock 33 Addresses need not be accessed ...

Page 17: ...An An 1 An 2 An 2 Dn 2 An 3 An 4 Qn Qn 3 Notes 34 In this depth expansion example B1 represents Bank 1 and B2 is Bank 2 each bank consists of one Cypress FLEx18 device from this data sheet ADDRESS B1 ADDRESS B2 35 ADS CNTEN BE0 BE1 OE LOW MRST CNTRST CNT MSK HIGH 36 Output state HIGH LOW or high impedance is determined by the previous cycle control signals 37 During No Operation data in memory at ...

Page 18: ...Switching Waveforms continued tCYC2 tCL2 tCH2 tHC tSC tHW tSW tHA tSA An An 1 An 2 An 3 An 4 An 5 tHW tSW tSD tHD Dn 2 tCD2 tOHZ READ READ WRITE Dn 3 Qn CLK CE R W ADDRESS DATAIN DATAOUT OE Qn 4 tCD2 tSA tHA tCH2 tCL2 tCYC2 CLK ADDRESS An COUNTER HOLD READ WITH COUNTER tSAD tHAD tSCN tHCN tSAD tHAD tSCN tHCN Qx 1 Qx Qn Qn 1 Qn 2 Qn 3 tDC tCD2 READ WITH COUNTER READ EXTERNAL ADDRESS ADS CNTEN DATAO...

Page 19: ...D CLK ADDRESS INTERNAL DATAIN ADDRESS tSA tHA CNTEN ADS CLK ADDRESS INTERNAL CNTEN ADS DATAIN ADDRESS CNTRST R W DATAOUT An Am Ap Ax 0 1 An Am Ap Q1 Qn Q0 D0 tCH2 tCL2 tCYC2 tSA tHA tSW tHW tSRST tHRST tSD tHD tCD2 tCD2 tCKLZ 42 RESET ADDRESS 0 COUNTER WRITE READ ADDRESS 0 ADDRESS 1 READ READ ADDRESS An ADDRESS Am READ Notes 40 CE0 BE0 BE1 LOW CE1 MRST CNT MSK HIGH 41 No dead cycle exists during c...

Page 20: ...CD2 INTERNAL ADDRESS An 1 An 2 An tCKHZ DATAOUT An Qn 3 Qn 1 Qn 2 An 3 An 4 tCKLZ tCA2 or tCM2 READBACK INTERNAL COUNTER ADDRESS INCREMENT EXTERNAL A0 A16 Notes 43 CE0 OE BE0 BE1 LOW CE1 R W CNTRST MRST HIGH 44 Address in output mode Host must not be driving address bus after tCKLZ in next clock cycle 45 Address in input mode Host can drive address bus after tCKHZ 46 An is the internal value of th...

Page 21: ...ORT ADDRESS R_PORT DATAOUT Notes 47 CE0 OE ADS CNTEN BE0 BE1 LOW CE1 CNTRST MRST CNT MSK HIGH 48 This timing is valid when one port is writing and other port is reading the same location at the same time If tCCS is violated indeterminate data is Read out 49 If tCCS minimum specified value then R_Port is Read the most recent data written by L_Port only 2 tCYC2 tCD2 after the rising edge of R_Port s...

Page 22: ...d tCH2 tCL2 tCYC2 CLK 3FFFD 3FFFF INTERNAL ADDRESS Last_Loaded Last_Loaded 1 tHCM COUNTER 3FFFE CNTINT tSCINT tRCINT 3FFFC CNTEN ADS CNT MSK tSCM Notes 50 CE0 OE BE0 BE1 LOW CE1 R W CNTRST MRST HIGH 51 CNTINT is always driven 52 CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value 53 The mask register assumed to have the value of 3FFFFh Feedback ...

Page 23: ...An 1 An 2 L_PORT ADDRESS Am Am 4 Am 1 7FFFF Am 3 R_PORT ADDRESS INTR tSA tHA tSINT tRINT Notes 54 CE0 OE ADS CNTEN LOW CE1 CNTRST MRST CNT MSK HIGH 55 Address 7FFFF is the mailbox location for R_Port of the 9Mb device 56 L_Port is configured for Write operation and R_Port is configured for Read operation 57 At least one byte enable BE0 BE1 is required to be active during interrupt operations 58 In...

Page 24: ...4 x 14 x 1 4 mm Pb Free 128K 18 2M 3 3V Synchronous CY7C0831AV Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C0831AV 167BBC 51 85141 144 Ball Grid Array 13 x 13 x 1 6 mm with 1 mm pitch Commercial CY7C0831AV 167AC 51 85100 120 Pin Thin Quad Flat Pack 14 x 14 x 1 4 mm CY7C0831AV 167AXC 120 Pin Thin Quad Flat Pack 14 x 14 x 1 4 mm Pb Free 133 CY7C0831AV 1...

Page 25: ...0837AV 133BBI 51 85141 144 Ball Grid Array 13 x 13 x 1 6 mm with 1 mm pitch Industrial Package Diagrams Figure 20 144 Ball FBGA 13 x 13 x 1 6 mm 51 85141 Ordering Information SEATING PLANE Ø0 50 144X 0 40 0 05 1 60MAX 0 70 0 05 A1 CORNER 11 00 1 00 13 00 0 10 13 00 0 10 1 00 11 00 F M J K L H G C D E B A 12 9 11 10 7 6 8 3 5 4 1 2 Ø0 05 M C Ø0 25 M C A B C M L K F H J G E D A B 1 12 11 2 10 3 9 4 ...

Page 26: ...CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0832BV CY7C0833AV Document 38 06059 Rev S Page 26 of 28 Figure 21 120 Pin Thin Quad Flatpack 14 x 14 x 1 4 mm 51 85100 Package Diagrams 51 85100 Feedback ...

Page 27: ...te to a certain location while another port is reading that location from Functional Description J 231813 WWZ See ECN Removed x36 devices CY7C0852 CY7C0851 from this datasheet Added 0 5M 1M and 9M x18 devices to it Changed title to FLEx18 3 3V 32K 64K 128K 256K 512K x18 Synchronous Dual Port RAM Changed datasheet to accommodate the removals and additions Removed general JTAG description Updated JT...

Page 28: ...re and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IM...