CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S
Page 8 of 28
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal mirror register is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this mirror
register. If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the mirror register. Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all ‘1s,’ which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all ‘1s’.
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment opera-
tions. Permitted values are of the form 2
n
– 1 or 2
n
– 2. From the
most significant bit to the least significant bit, permitted values
have zero or more ‘0s,’ one or more ‘1s,’ or one ‘0.’ Thus 3FFFF,
003FE, and 00001 are permitted values, but 3F0FF, 003FC, and
00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid t
CM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) is three-stated.
Figure 3
on page 9 shows a
block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is ‘0,’ the
counter increments by two. This may be used to connect the x18
devices as a 36-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 36-bit data in even memory locations, and the
other half in odd memory locations.
[+] Feedback
