STK16C88
Document Number: 001-50595 Rev. **
Page 2 of 14
Pin Configurations
Figure 1. Pin Diagram - 28-Pin PDIP
Table 1. Pin Definitions - 28-Pin PDIP
Pin Name
Alt
IO Type
Description
A
0
–A
14
Input
Address Inputs.
Used to select one of the 32,768 bytes of the nvSRAM.
DQ
0
-DQ
7
Input or
Output
Bidirectional Data IO lines
. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW
. When the chip is enabled and WE is LOW, data on the
IO pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW
. When LOW, selects the chip. When HIGH, deselects the
chip.
OE
G
Input
Output Enable, Active LOW
. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
V
SS
Ground
Ground for the Device
.
The device is connected to ground of the system.
V
CC
Power Supply
Power Supply Inputs to the Device
.
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