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CY4636 WirelessUSB™ LP Keyboard Mouse Reference Design Kit User Guide, Doc. # 001-70355 Rev. *A
Hardware
Table 4-2. CY7C63803 Chip Pin Details
Pin
Name
Description
1
P0.6/TIO1
GPIO Port 0 bit 6. Configured individually. Alternate function Timer capture inputs or Timer output TIO1
2
P0.5/TIO0
GPIO Port 0 bit 5. Configured individually. Alternate function Timer capture inputs or Timer output TIO0
3
P0.4/INT2
GPIO Port 0 bit 4. Configured individually. Optional rising edge interrupt INT2.
4
P0.3/INT1
GPIO Port 0 bit 3. Configured individually. Optional rising edge interrupt INT1.
5
P0.2/INTO
GPIO Port 0 bit 2. Configured individually. Optional rising edge interrupt INT0.
6
P0.1
GPIO Port 0 bit 1. Configured individually. On CY7C638xx and CY7C63310, clock output when config-
ured as Clock Out.
7
P0.0
GPIO Port 0 bit 0. Configured individually. On CY7C638xx and CY7C63310, external clock input when
configured as Clock In.
8
V
SS
Ground
9
P1.0/D+
GPIO Port 1 bit 0/USB D+ [1] If this pin is used as a general purpose output, it draws current. This pin
must be configured as an input to reduce current draw.
10
P1.1/D–
GPIO Port 1 bit 1/USB D– [1] If this pin is used as a general purpose output, it draws current. This pin
must be configured as an input to reduce current draw.
11
V
CC
Supply
12
P1.2/VREG
GPIO Port 1 bit 2. Configured individually. 3.3V if regulator is enabled. (The 3.3 V regulator is not avail-
able in the CY7C63310 and CY7C63801.) A 1-mF min, 2-mF max capacitor is required on Vreg output.
13
P1.3/SSEL
GPIO Port 1 bit 3. Configured individually. Alternate function is SSEL signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the CY7C63310, 3.3 V I/O is still available.
14
P1.4/SCLK
GPIO Port 1 bit 4. Configured individually. Alternate function is SCLK signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the CY7C63310, 3.3 V I/O is still available.
15
P1.5/SMOSI
GPIO Port 1 bit 5. Configured individually. Alternate function is SMOSI signal of the SPI bus TTL volt-
age thresholds. Although Vreg is not available with the CY7C63310, 3.3 V I/O is still available.
16
P1.6/SMISO
GPIO Port 1 bit 6. Configured individually. Alternate function is SMISO signal of the SPI bus TTL volt-
age thresholds. Although Vreg is not available with the CY7C63310, 3.3 V I/O is still available.