Built-In BIOS Setup Program
The available options are :
x222
DRAM Write Burst Determines the timing for burst write to the
cache. If your DRAM type is
DRAM, we suggest you select x222
(EDO) timing to get a better performance.
The available options are :
-x333
DRAM
Select The selection of the
fast path for read
cycles. The available options are :
-Enabled
CPU-To-PC1 IDE Posting When disabled, the Read/Write cycles are
treated as normal I/O write transactions. The available options are :
-Disabled
DRAM Read
Write When this option is enabled, it enables
the read-around-write capability for the DRAM Global Write Buffers.
The available options are :
-Disabled
Burst Write Combining When this option is enabled, the PAC is
allowed to combine back-to-back sequential CPU-to-PC1 writes into a
single
write burst. The available options are :
-Disabled
PCI-To-DRAM Pipeline The selection of complete or restricted
lo-DRAM pipelining.
options are
-Disabled
Built-In BIOS Setup Program
System BIOS Cacheable Allows caching of the different segments
where there is system BIOS shadowing. The available options are :
-Enabled (default)
-Disabled
Video BIOS Cacheable Allows caching of the different segments where
there is video BIOS shadowing. The available options are :
-Enabled (default)
-Disabled
Bit I/O Recovery Time -Defines the S-bit I/O recovery time with one
of the following system clock options. The available options are :
1 (default)
16 Bit I/O Recovery Time -Defines the
I/O recovery time with
one of the following system clock options. The available options are :
1 (default)
Memory Hole At
Enables this option to reserve the certain
space in memory for ISA cards. The available options are:
-Disabled (default)
-Enabled
Passive Release Enable
disables the passive release mechanism
encoded on the
Signal when
to ISA/IDE
is
a
master. The available options are:
-Enabled
Delayed Transaction Enable or disables the delayed transaction
mechanism when
to
Xecelerator” is the target of a PCI
transaction. The available options are:
Enabled
