61
Main DEC Circuit
MP01
DVD-2000 (USA)
A2
3
5
Monday, March 04, 2002
Title
Size
Document Number
Rev
Date:
Sheet
of
+5VD
+3.65V
+3.65V
+3.65V
+5VD
+5VD
+5VD
+5VD
+3.65V
+3.2V
+3.65V
+5VALL
+5VD
+3.65V
+5VD
DB[0..15]
DD0
DD13
DIORDY
DWR#
DIOCS16#
DACS1#
DD14
DD12
DD10
DD1
DD7
DD6
DD3
DA2
DA0
DD8
DD11
DD9
DRST#
DD15
DD2
DD4
DD5
DRD#
DACS3#
DIRQ
DA1
LCS2#
XIN
LOE#
WRLL#
LCS3#
DB1
DB2
DB7
DB4
DB9
DB15
DB3
DQMX
DB5
HOST_DATA
CAS#
WE#
HOST_CS
I2C_DATA
RAS0#
DB13
DB0
I2C_CLK
DB6
DB12
DB10
HOST_CLK
DB11
DB14
DB8
LD3
LD2
LD7
LD4
LD0
LD5
LD1
LD6
LA19
LA4
LA14
LA3
LA7
LA21
LA18
LA6
LA11
LA0
LA10
LA2
LA12
LA1
LA16
LA17
LA9
LA5
LA8
LA13
LA15
LA20
LD[0..7]
LCS1#
RST#
DSCK
MCLK
XIN
YUV2
YUV0
YUV3
YUV6
YUV4
YUV5
YUV1
YUV7
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
WRLL#
LCS3#
LOE#
LD1
LD4
LD5
LD3
LD2
LD0
MRSTB
LCS3#
LOE#
LA10
LA4
LA17
LA5
LA14
LA6
LA9
LA16
LA19
LA15
LA1
LA3
LA8
LA21
LA11
LA13
LA7
LA0
LA18
LA2
LA12
WRLL#
LD6
LD7
LA[0..21]
CAS#
WE#
RAS0#
DSCK
MA11
DQMX
DB12
DB5
DB10
DB9
BA1
DB3
DB15
DB14
DB1
DB2
DB0
DB7
DB8
DB11
DB13
DB6
DB4
MA10
MA6
MA0
MA[0..11]
MA7
MA1
MA8
MA9
MA8
MA11
MA9
MA7
MA3
MA3
MA5
MA2
MA6
MA10
BA1
MA0
MA1
MA4
MA4
MA5
MA2
+5VDD
U207C
74HCU04
5
6
14
7
U208C
74HC04
5
6
14
7
R122
4.7K
R120
4.7K
D201
1N5817(open)
R276
open
R121
4.7K
U201
W27E040/080
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
13
14
15
17
18
19
20
21
2
22
24
31
30
1
32
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
A16
CE
O E
A18
A17
A19
VCC
GND
J201
ROM EMULATOR(open)
1
2
3
4
RESET CLK/CE1
WE ADDR/CE1
C218
104
CE102
10u/16V
R231
10
R271
3.3K
C233
104
R123
OPEN
C234
104(open)
TP204
TP104
TP201
U204
AT24C02A
1
2
3
4
5
6
7
8
A0
A1
A2
VSS
SDA
SCL
NC
VCC
TP105
U101
ES4318
121
122
123
124
125
126
127
128
129
53
2
54
1
55
3
56
4
57
5
58
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VCC
HD0/DCI[0]
HD1/DCI[1]
HD2/DCI[2]
HD3/DCI[3]
HD4/DCI[4]
HD5/DCI[5]
HD6/DCI[6]
VSS
DMA0
LA4
DMA1
VCC
DMA2
LA5
DMA3
LA6
DMA4
LA7
DMA5
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VCC
LA17
LA18
LA19
LA20
LA21
RESET
TDMDX/RSEL
VSS
VCC
TDMDR
TDMCLK
TDMFS
TDMTSC
TWS/SEL_PLL1
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL2
TSD2
TSD3
MCLK
TBCK
SPDIF_DOBM
SPDIF_DIBM
VSS
VCC
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
VCC
VSS
VCC
VSS
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
VSS
VCC
DCAS
DOE/DSCK_EN
DWE
DRAS0
DRAS1
DRAS2
VCC
VSS
DB0
DB1
DB2
DB3
DB4
DB5
VCC
VSS
DB6
DB7
DB8
DB9
DB10
DB11
VSS
VCC
DB12
DB13
DB14
DB15
DCS1
VSS
VCC
DCS0
DQM
DSCK
VSS
VCC
CLK
YUV0
YUV1
YUV2
YUV3
YUV4
VCC
VSS
YUV5
YUV6
YUV7
PCLK2XSCN
PCLKQSCN
VSSCN
HSSCN
VSS
VCC
HD7/DCI[7]
HD8/DCI_FDS
HD9
HD10
HD11
HD12
HD13
VSS
VCC
HD14
HD15
HWRQ/DCI_REQ
HRDQ
HIRQ/DCI_ERR
HRST
HIORDY
VSS
VCC
HWR/DCI_CLK
HRD/DCI_ACK
HIOCS16
HCS1FX
HCS3FX
HA0
HA1
VSS
VCC
HA2
VPP
AUX0
AUX1
AUX2
VSS
VCC
AUX3
AUX4
AUX5
AUX6
AUX7
LOE
VSS
VCC
LCS0
LCS1
LCS2
LCS3
VSS
LD0
LD1
LD2
LD3
LD4
VCC
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VCC
LD12
LD13
LD14
LD15
LWRLL
LWRHL
VSS
VCC
NC
NC
LA0
LA1
LA2
LA3
VSS
TP205
TP202
C219
47p
C220
104
C206
104
C212
104
C106
104
C103
104
C105
104
C104
104
C204
104
C207
104
C109
104
C102
104
C213
104
C107
104
C214
104
C111
104
C202
104
C209
104
C101
104
R270
220
R262
220
R130
47K
R129
47K
C108
104
C208
104
C203
104
C201
104
C205
104
C211
104
C110
104
C215
104
R273
open
R214
33
R217
33
R221
47
R223
47
R207
33
R222
47
R225
47
R219
33
R215
33
R220
47
R218
33
R230
33
C112
104
C114
104
C113
104
R208
33
R229
33
R210
33
R206
33
R213
33
R224
47
R216
33
C116
104
C115
104
C117
104
C118
104
R209
33
R211
33
R226
47
R212
33
R227
47
R204
33
R228
33
R205
33
R242
1K
R106
10
R108
10
R112
10
R107
10
R104
10
C126
open
R111
10
R103
10
R115
33
R118
33
R114
33
R105
10
R101
10
R109
10
L201
FB2012
C122
OPEN
R241
1K
R113
33
R102
10
R110
10
R117
33
R202
4.7K
R277 1M
39LF040
U209
SST39VF040(open)
20
19
18
17
16
15
14
13
3
2
31
1
12
4
5
11
10
6
9
21
22
23
25
26
27
28
29
32
7
8
24
30
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
D0
D1
D2
D3
D4
D5
D6
D7
O E
WE
VDD
VSS
CE
C231
open
C128
104
C229
33p
C235
open
R235
0
U208F
74HC04
13
12
14
7
R234 1M
C228
22p
C227
33p
R261
1M
R131
0
TP103
TP102
TP101
L202
FB2012
U208B
74HC04
3
4
14
7
X201
27MHz
U208A
74HC04
1
2
14
7
U102
K4S641632D
1
2
4
6
5
7
3
8
10
12
11
13
49
15
16
17
18
19
35
22
23
24
25
26
27
28
29
30
31
32
33
34
36
37
38
39
40
9
42
44
52
45
47
43
48
50
46
51
53
54
14
41
20
21
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
VSS
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC
VDDQ
DQ8
DQ9
VSSQ
DQ10
DQ11
VDDQ
DQ12
DQ13
VSSQ
DQ14
DQ15
VSS
VDD
VSS
BA0
BA1
TP206
TP207
C210
104
U207F
74HCU04
13
12
14
7
R232
33
CE201
10u/16V
C232
104
TP208
CE101
10u/16V
U207A
74HCU04
1
2
14
7
U207D
74HCU04
9
8
14
7
U207B
74HCU04
3
4
14
7
U207E
74HCU04
11
10
14
7
C124
27p
C129
27p
C125
27p
CE202
10u/16V
R274
0
R275
open
R272
0
DRST#
DRD#
DWR#
DD[0..15]
DIORDY
DACS1#
DIOCS16#
DACS3#
DIRQ
DA[0..2]
VFD_CLK
ASDATA_DVD
HOST_CS
HOST_DATA
VSYNC
HSYNC
YUV[0..7]
HOST_CLK
I2C_DATA
LRCK_DVD
VFD_DATA
I2C_CLK
BCLK_DVD
MCLK
VFD_STB
MRSTB
SPDIF
27MHz
not insert
SST39VF040 Use only
Debuging port
EPROM --> R272, R275, R274 : Open
EPROM --> R273, R276 : 0 ohm
Flash --> R273, R275, R276 : Open
Flash --> R272, R274 : 0 ohm
8 M --> R272, R274, R276 : Open
8 M --> R273, R275 : 0 ohm
DIP Type
Schematic Diagrams
11-1-3 Main PCB MPEG Decoder Block Schematic diagram
2
3
4
5
1
Summary of Contents for DVC-T6300N
Page 10: ...10 2 1 3 NTSC PAL Digital Video Encoder AD7170 Component Descriptions ...
Page 11: ...11 Component Descriptions ...
Page 12: ...12 Component Descriptions ...
Page 14: ...14 Functional Description Component Descriptions ...
Page 15: ...15 Component Descriptions Pinout Diagram ...
Page 18: ...18 Block Diagram Component Descriptions 2 1 5 DIGITAL TO ANALOG STEREO AUDIO CONVERTER CS4391 ...
Page 19: ...19 Component Descriptions ...
Page 20: ...20 Component Descriptions ...
Page 21: ...21 Component Descriptions ...
Page 28: ...28 Component Descriptions ...
Page 30: ...30 Component Descriptions ...
Page 31: ...31 Component Descriptions ...
Page 54: ...54 9 PCB Diagrams 9 1 Main PCB Top ...
Page 55: ...55 PCB Diagrams 9 2 Main PCB Bottom ...
Page 56: ...56 9 3 Front PCB Top 9 4 Front PCB Bottom PCB Diagrams ...
Page 57: ...57 9 5 SMPS PCB Top 9 6 SMPS PCB Bottom PCB Diagrams ...
Page 58: ...58 10 Wiring Diagram ...
Page 65: ...65 11 3 SMPS PCB Schematic Diagram 11 3 SMPS PCB Schematic diagram ...
Page 66: ...66 1 27MHz 2 ROM DATA BUS 3 RAM DATA BUS 4 12C CLK 5 12C DATA 6 HSYNC 12 Oscillograms ...
Page 67: ...67 7 VSYNC 8 BCLK DVD 9 LRCK DVD 10 TSDO 11 MCLK 12 HOST DATA Oscillograms ...
Page 68: ...68 13 HOST CLK 14 HOST CS 15 MC DACO 16 MD DACO 17 VFD DATA 18 VFD STB Oscillograms ...
Page 70: ...70 MEMO ...