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Theory of Operation
X64-AN Quad User's Manual
Sync on Composite Video
Vertical Sync (VS) and horizontal sync (HS) signals are extracted from the composite video output
signal by the sync extractor The PLL receives the stripped horizontal sync and outputs a pixel clock
which is line-locked to the incoming video. The pixel clock then drives the ADC timing to digitize
video and also generates frame timing. The PLL, which maintains a frequency stable pixel clock, is
programmed based on the timing requirements of the incoming video.
Analog Composite
Video
Pixels
Valid Pixels
A/D
LUT
Cropper
Sync
Extractor
PLL
VS
HS
Pixel Clock
Figure 16: Composite Video Synchronization Block Diagram
Synchronization on composite video is commonly used for standard RS-170 and CCIR cameras as
well as for many non-standard cameras. The following table shows the Sapera timing parameters used
by the synchronization hardware. Use the Sapera CamExpert utility to program camera timings and
create camera files for any non-standard camera usable with the X64-AN Quad.
Sapera parameters for Sync on Composite Video:
CORACQ_PRM_SYNC = CORACQ_VAL_SYNC_COMP_VIDEO
CORACQ_PRM_HSYNC: Size of horizontal sync pulse
CORACQ_PRM_HBACK_PORCH: Size of horizontal back porch
CORACQ_PRM_HACTIVE: Number of valid pixels per line
CORACQ_PRM_HFRONT_PORCH: Size of horizontal front porch
CORACQ_PRM_VSYNC: Size of vertical sync pulse
CORACQ_PRM_VBACK_PORCH: Size of vertical back porch
CORACQ_PRM_VACTIVE: Number of valid line from camera
CORACQ_PRM_VFRONT_PORCH: Size of vertical front porch