X64-AN Quad User's Manual
Theory of Operation
51
On-board Memory
The onboard memory behaves as a temporary buffer between the camera interface and the host PCI-
bus system. The default total onboard memory capacity is 128MB. There is a maximum frame size of
4094 x 16,777,215. Two or more frames are stored within onboard memory for double buffering.
Onboard memory allows the capture from cameras requiring a bandwidth exceeding the PCI-32
maximum of 132MB/second (PCI-64 maximum burst transfer rates are greater).
The
X64-AN Quad
supports the pixel format of 8-bit monochrome.
PCI Bus DMA Controller
The PCI Bus DMA controller has scatter/gather support to reduce CPU usage to a minimum. Host
system memory allocated for frame buffers is virtually contiguous but physically scattered throughout
all available memory. The buffer descriptor list is maintained in host memory.
The PCI Bus DMA controller maximum performance is specified independently from the analog
acquisition front end of the
X64-AN Quad
. The following table defines the PCI Bus DMA controller
maximum data transfer rates
Bus
Sustained Transfer
Max. Burst Transfer
PCI-32
120 MB/second
132 MB/second
PCI-64
320 MB/second
528 MB/second
Trigger to Image Reliability
Trigger-to-image reliability incorporates all stages of image acquisition inside an integrated controller
to increase reliability and simplify error recovery. The trigger-to-image reliability model brings
together all the requirements for image acquisition to a central management unit. These include signals
to control camera timing, on-board frame buffer memory to compensate for PCI bus latency, and
comprehensive error notification. If the X64-AN Quad detects a problem, the application can take
appropriate action to return to normal operation.
The X64-AN Quad is designed with a robust ACU (Acquisition and Control Unit). The ACU monitors
in real-time, the acquisition state of the input plus the DTE (Data Transfer Engine) which transfers
image data from on-board memory into PC memory. In general, these management processes are
transparent to end-user applications. With the X64-AN Quad, applications ensure trigger-to-image
reliability by monitoring events and controlling transfer methods as described below:
