VFD500 high performance vector control frequency inverter user manual Chapter 5 function code table
P07.11
Output logic negative
Define as per bit O:off;1:on(negative)
Bit0:DO1
Bit1:DO2
Bit2:Relay 1
Bit3: Relay 2
Bit4: DO3;Bit5: DO4 Bit6: DO5; Bit7: DO6
Bit8: VDO1;Bit9: VDO2
Notice:posive logic equivalent to Normal open
point
And negative logic equivalent to Normal close
point
0
☆
P07.12
DO1 effective delay time
0.000s
~
30.000s
0.000s
☆
P07.13
DO1 ineffective delay time
0.000s
~
30.000s
0.000s
☆
P07.14
DO2 effective delay time
0.000s
~
30.000s
0.000s
☆
P07.15
DO2 ineffective delay time
0.000s
~
30.000s
0.000s
☆
P07.16
Relay 1 effective delay
time
0.000s
~
30.000s
0.000s
☆
P07.17
Relay 1 ineffective delay
time
0.000s
~
30.000s
0.000s
☆
P07.18
Relay 2 effective delay
time
0.000s
~
30.000s
0.000s
☆
P07.19
Relay 2 ineffective delay
time
0.000s
~
30.000s
0.000s
☆
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Summary of Contents for VFD500 Series
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