Page 22 of 32
Rev 0.95
6
bInterlock1_9
eIL_Interlock2_09
Choke over temp
7
bInterlock1_10 eIL_Interlock2_10
Transistor over temp
8
bInterlock1_11 eIL_Interlock2_11
MPS water flow
9
bInterlock1_12 eIL_Interlock2_12
Earth leak
10
bInterlock1_13 eIL_Interlock2_13
Preregulation error
11
bInterlock1_14 eIL_Interlock2_14
Regulation error
12
bInterlock1_15 eIL_Interlock2_15
MPS spare 1
13
bInterlock1_16 eIL_Interlock2_16
MPS spare 2
Table 5 Register 2
4.3.1.1.
Register 3, bit 12
Command: STATus:OPERation:REG3.
Bit
Input
Signal
(Index)
Interpretation/default configuration
0
bInterlock2_1
eIL_Interlock3_01
Magnet over temp
1
bInterlock2_2
eIL_Interlock3_02
Magnet flow interlock
2
bInterlock2_3
eIL_Interlock3_03
External 1
3
bInterlock2_4
eIL_Interlock3_04
External 2
4
bInterlock2_5
eIL_Interlock3_05
External 3
5
bInterlock2_6
eIL_Interlock3_06
External 4
6
bInterlock2_7
eIL_Interlock3_07
MPS spare 3
7
bInterlock2_8
eIL_Interlock3_08
MPS spare 4
8
bInterlock2_9
eIL_Interlock3_09
MPS spare 5
9
bInterlock2_10 eIL_Interlock3_10
MPS spare 6
10
bInterlock2_11 eIL_Interlock3_11
Status spare 1
11
bInterlock2_12 eIL_Interlock3_12
Status spare 2
12
bInterlock2_13 eIL_Interlock3_13
Status spare 3
13
bInterlock2_14 eIL_Interlock3_14
5% transistor fail
Table 6 Register 3