2 Theory of Operation
2-16
05/04 1006-0453-000
A system reset will occur between 62.5 msec and 250 msec if no legal toggle
addresses occur by that time. Multiple level 7 interrupts will occur prior to a
reset. The output of this watchdog is connected to IRQ7 on the 68340
processor.
Error response sequence
Errors detected by either watchdog are handled in the following sequence:
• At the first detection of any error, a watchdog responds by issuing an IRQ7
interrupt.
• If the exception handler software for IRQ7 cannot correct the error, then the
next detection of an error causes a soft system reset.
• If the error still cannot be corrected, then an audio alarm sounds
(independent of processor interaction) and a cyclic soft reset continues until
the error is corrected or the system is powered down.
DATA acquisition
The data acquisition system for the Aestiva 7900 Ventilator consists of two
major building blocks. The first is an analog to digital converter (ADC) system
and the second is a digital to analog converter (DAC) system.
This portion of the Aestiva 7900 Ventilator allows the microprocessor to
interface with valves and pressure transducers. The data acquisition system is
also used for internal monitoring of safety relevant signals.
The ADC system is designed to meet the following specifications:
The DAC system is designed to meet the following specifications:
Resolution
12 Bits
Input Voltage Range
0 - 4.095 Volts (1mV/LSB)
Number of Channels
24
Total Conversion Time
8 to 8.63 µsec max
Integral Nonlinearity
± 1 LSB max
Differential Nonlinearity
± 1 LSB max (guaranteed monotonic)
Full-Scale Error
± 6 LSB max
Unipolar Offset Error
± 3 LSB max
Resolution
12 Bits
Number of Channels
1
Settling time to 0.01%
30 µsec max
Output Voltage Range
0 - 4.095 Volts (1mV/LSB)
Integral Nonlinearity
± 1 LSB max
Differential Nonlinearity
± 1 LSB max (guaranteed monotonic)
Full-Scale Error
± 9 LSB max
Zero-Scale Error
+ 4 LSB max
Summary of Contents for Aestiva 7900 SmartVent
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