Description
PSM-500/500L/500LT SCPC Satellite Modem
PSM-500/500L/500LT - Rev. 0.91
Page 1-12
1.2.4 Control Processor
A single microprocessor manages all monitor, control and communications functions on the modem
board. The processor continuously monitors all onboard status signals.
The modem control processor uses external address and data buses to connect to external Flash
PROM containing the instruction code. The processor uses both internal and external RAM for all
operations and maintains configuration and permanent parameters in parallel EEPROM. The
processor also connects to the FEC, the custom ASICs, the DSP processor, the front panel, and
various onboard peripheral functions via the address and data bus.
The control processor also maintains a serial peripheral interface to connect to several onboard
peripherals. These include external D/A converters holding calibration and current analog settings,
identification EEPROMs on option and interface cards and step synthesizers.
The control processor also contains an internal 12-Channel 10-bit A/D converter for gathering
analog information from various onboard monitored points including the phase locked loop tuning
voltages.
Digital I/O used to monitor and control the modem is handled mainly through the DSP circuits and
their interface to the processor. Such parameters as the current Eb/No and receive offset frequency
information are read by the processor from the DSPs while most configuration information is written
to the DSPs.
The control processor uses a full-duplex Universal Asynchronous Receiver/Transmitter (UART) for
communications with either the RS–232 / RS–485 remote command port or with a separate VT100
type “console” terminal device connected to the modem. In addition a USB control interface is
provided.
The control processor has provisions for communicating with another PSM-500 modem for
implementation of Automatic Uplink Power Control (AUPC). The channel for this communications is
normally provided by equipping the unit with the optional IBS multiplexer interface card.
1.2.5 Acquisition Processor
The acquisition processor, a Texas Instruments 320C5xxx Digital Signal Processor, manages the
receive signal acquisition and lock functions to achieve fast acquisition performance at low data
rates. This DSP is controlled by the control processor via a communications protocol managed
through a special bi-directional parallel interface to the main processor.
The signal acquisition DSP accepts sampled data from the receive chain A/D Converters and
mathematically determines the location of the incoming carrier. This is accomplished in a multi–step
process which continues to narrow down the exact frequency until it is known within the lock range
of the PLL demodulator. At data rates below 16 kbps this process is more than an order of
magnitude faster than a standard sweep method. Typical signal acquisition times at 16 kbps QPSK
are 0.2 seconds using the acquisition processor vs. over 20 seconds using a standard sweep.
1.2.6 Standard Data Interface
The standard Interface in the PSM-500 is built onto the main PWB and contains the drivers and
receivers for one of five possible data interface standards (seven including minor variations of each).
All interface standards are selected under program control via the front panel or remote control. Five
of these standards are common interfaces used in the communications industry:
•
RS-449, terminated and un-terminated
•
V.35,
•
V.36
•
Synchronous RS-232 (Limited to 128 kbps by drivers and receivers.)
•
EIA-530 and EIA-530A
•
Asynchronous RS-232 (Limited to 115 kbps by various protocols).
