D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
6.1
Carrier board mating connector J1
J1 – ODD [1 - 139]
Pin
Pin Name
Internal Connections
Ball/
pin #
Supply
Group
Type
Voltage
Note
J1.1
DGND
DGND
-
G
J1.3
DGND
DGND
-
G
J1.5
USB0_DM
CPU.USB0_DM
AH11
D, I/O
J1.7
UART0_RXD
CPU.UART0_RXD
AH5
I
J1.9
VBAT
PMIC.VBACKUP
D7
S
If not used, VBAT must be externally
connected to GND.
J1.11
MDIO_MDCLK
CPU.MDCLK/GP1[11]
H28
I/O
Module mount option
UART4_RXD/GP3_1
CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[
0]/VIN[1]A_D[1]/UART4_RXD/GP3[1]
AG25
I/O
J1.13
ADC_GND
DGND
-
G
J1.15
ADC0_IN
TSC.IN1
16
A
J1.17
USB0_ID
CPU.USB0_ID
AG10
A I
J1.19
UART0_RTSn/DCAN1_RX
CPU.UART0_RTSn/UART4_TXD/DCAN1_RX/
SPI[1]_SCS[2]n/SD2_SDCD
AF5
I/O
J1.21
UART0_CTSn/DCAN1_TX
CPU.UART0_RTSn/UART4_RXD/DCAN1_TX/
SPI[1]_SCS[3]n/SD0_SDCD
AE6
I/O
J1.23
VIN0A_D16/CAM_D8
CPU.VIN[0]A_D[16]/CAM_D[8]/I2C[2]_SCL/
GP0[10]
AA21
I/O
J1.25
VIN0A_D17/CAM_D9
CPU.VIN[0]A_D[17]/CAM_D[9]/EMAC[1]_R
MRXER/GP0[11]
AB21
I/O
J1.27
VIN0A_D18/CAM_D10
CPU.VIN[0]A_D[18]/CAM_D[10]/EMAC[1]_
RMRXD[1]/I2C3[3]_SCL/GP0[12]
AF20
I/O
J1.29
VIN0A_D19/CAM_D11
CPU.VIN[0]A_D[19]/CAM_D[11]/EMAC[1]_
RMRXD[0]/I2C3[3]_SDA/GP0[13]
AF21
I/O
J1.31
VIN0A_D20/CAM_D12
CPU.VIN[0]A_D[20]/CAM_D[12]/EMAC[1]_
RMCRSDV/SPI[3]_SCS[0]n/GP0[14]
AC17
I/O
J1.33
VIN0A_D21/CAM_D13
CPU.VIN[0]A_D[21]/CAM_D[13]/EMAC[1]_
RMTXD[0]/SPI[3]_SCLK/GP0[15]
AE18
I/O
J1.35
DGND
DGND
-
G
J1.37
SPI1_D0/GP1_26
CPU.SPI[1]_D[0]/GP1[26]
AA6
I/O
J1.39
TSC_XP
TSC.X+
2
I
Please consider the use of ESD
August, 2014
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