D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
J2 – EVEN [2-140]
Pin
Pin Name
Internal Connections
Ball/pi
n #
Supply
Group
Type
Voltage
Note
J2.122 VIN0A_FLD/UART5_RXD
CPU.VIN[0]A_FLD/VIN[0]B_VSYNC/UAR
T5_RXD/I2C[2]_SCL/GP2[1]
AA20
I/O
1.8V/3.3V
J2.124 USBP1
USB1.D+
D, I/O
J2.126 USBM1
USB1.D-
D, I/O
J2.128 UART3_RXD/SD1_POW
CPU.UART0_DCDn/UART3_RXD/SPI[0]
_SCS[3]n/I2C[2]_SCL/SD1_POW/GP1[2
]
AH4
I/O
1.8V/3.3V
J2.130 UART3_CTSn
CPU.UART0_DTRn/UART3_CTSn/UART
1_TXD/GP1[4]
AG2
I/O
1.8V/3.3V
J2.132 VIN1A_D4/GP3_4
CPU.VOUT[1]_B_CB_C[7]/EMAC[1]_MR
XD[3]/VIN[1]A_D[4]/UART3_TXD/GP3[
4]
AC25
I/O
1.8V/3.3V
J2.134 USBP2
USB2.D+
D, I/O
J2.136 USBM2
USB2.D-
D, I/O
J2.138 3.3V
+3V3
-
S
J2.140 DGND
DGND
-
G
6.3
CPU module mount options
Some pins can be configured for different functions through mounting options. The rows into
the table appear as the following:
J2.78
MCA2_AFSX/GP0_11
CPU.MCA[2]_AFSX/GP0[11]
AA5
I/O
Module mount option
CVDD_DSP
MTR
-
O
The row content is split in two: the default pin configuration is the upper one (eg
TPS_PWRON); the optional pin configuration is the lower one (eg EMU1).
August, 2014
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