D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
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Asynchronous SRAM-like memories and application-specific
integrated circuit (ASIC) devices
●
Asynchronous, synchronous, and page mode (only available
in non-multiplexed mode) burst NOR flash devices
●
NAND Flash (with BCH and Hamming Error Code
Detection)
●
Pseudo-SRAM devices
●
The GPMC includes flexible asynchronous protocol control to
interface to SRAM-like memories and custom logic (FPGA,
CPLD, ASICs, etc.).
●
Other supported features include:
●
8/16-bit wide multiplexed address/data bus
●
512 MBytes maximum addressing capability divided among
up to eight chip selects (
seven
available on DIDO
connectors – GPMC_CS[7] is reserved for on-board NAND
memory).
●
Non-multiplexed address/data mode
●
Pre-fetch and write posting engine associated with system
DMA to get full performance from NAND device with
minimum impact on NOR/SRAM concurrent access.
DIDO provides up to 8-bit for data and 16 bit for addresses.
Please note that, when enabling the EMAC1 interface (see
7.5.3) the address bus is limited to bits GPMC_A[0] to
GPMC_A[4].
The following table describes the interface signals:
Connector Pin
Pin
name
Function
Notes
GPMC_CLK
J2.61
GPMC Clock
GPMC_CS[6]
J2.59
GPMC Chip Select #6
GPMC_CS[5]
J2.61
GPMC Chip Select #5
GPMC_CS[4]
J2.53
GPMC Chip Select #4
GPMC_CS[3]
J2.50
GPMC Chip Select #3
GPMC_CS[2]
J2.53
GPMC Chip Select #2
GPMC_CS[1]
J2.48
GPMC Chip Select #1
GPMC_CS[0]
J2.51
GPMC Chip Select #0
GPMC_WE
J2.57
GPMC Write Enable
GPMC_OE_RE
J2.56
GPMC Output Enable
August, 2014
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