Data Device Corporation
BU-65570/2i Manual
20
HARDWARE OPERATION
GENERAL
The BU-65572iX is the next generation DDC PCI Tester/Simulator which
can simultaneously simulate a MIL-STD-1553 BC, all RTs, and an
intelligent MT simultaneously on two 1553 buses.
Full error detection features are provided in all modes of operation. In
addition, user specified errors
including bit count and Manchester II
errors may be injected in BC and any of the emulated RT modes.
Operational characteristics of the BU-65572iX such as output voltage
level, bus termination, and coupling configuration are all software
controllable using functions provided in the software library.
BUS CONTROLLER MODE
The BU-65572iX Bus Controller supports all MIL-STD-1553B message
formats. Up to 1024 unique receive, transmit, mode code, and RT to RT
messages may be defined at one time for each of the installed channels.
A frame can contain up to 1024 unique messages.
Programmable attributes within a message include time to next
message, bus (channel A or channel B), intermessage routines, and
injected error. The time to next message defines the time from the start
of the present message to the start of the next message. The time to
next message is programmable up to 65,535 msec in 1-
µ
sec
increments.
Minor And Major Frames
The execution of messages is controlled by a message list referred to as
a frame. The frame specifies the contents and timing of complete
communication runs by the BC. Each entry in the frame is either a
reference to a message or a special frame symbol. The entire frame is
referred to as a major frame and is divided into minor frames each of
equal time duration.
Loading message ID handles into an U16BIT array specifies a frame.
Each message ID uniquely identifies a message that was previously
defined by the function ddcDefMessage (see BU-69068 manual). Other
elements that can be placed into a frame list are ‘Frame Symbols’. The
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
