Cores
CCDs x CCXs x Cores/CCX
NPSx options - Single processor
16
2x2x4
2, 1
16
4x2x2
4, 2, 1
8
4x2x1
4, 2, 1
8
2x2x2
2, 1
NOTE:
If the system configuration does not support an NPS profile, the options are not displayed until the configuration
changes.
NOTE:
If there is a memory training failure, configuration change, or processor swap that no longer supports a specific
NPS profile, an error message is displayed at the end of POST and logged in the LifeCycle Controller.
Interleaving option
Based on the NPSx selection, the PSP firmware selects the corresponding preferred memory interleaving. If the memory configuration
does not allow the preferred option (Example: a channel is not populated or one or more DIMMs on a channel does not initialize or train
properly), the pre-BIOS firmware selects the corresponding alternate memory interleaving option.
Table 42. Interleaving Options Based on NPSx
NPSx
Preferred
Alternate
4
2-channel
None
2
4-channel
2-channel
1
8-channel
4-channel, 2-channel
Two channel interleaving (per quadrant) - NPS4 and fallback for NPS2/1/0
•
This interleaves two channels in each quadrant.
•
Does not require the memory to be equal on both channels of a quadrant. Any non-symmetrical DIMM is stacked on top.
•
Any quadrant where one of the two channels is not populated is not interleaved.
•
There is no alternate, as all configurations can be mapped into this mode.
Four channel interleaving (per half-socket) - NPS2
•
This interleaves the four channels on the left or right half of a socket. As an alternative option from NPS1 only, the four channels {CS
A, B, C, D} may be interleaved.
•
Requires all four channels to be populated with equal size memory.
•
There is no requirement that the two halves have equal size memory with respect to each other.
•
The system has support for one half to have no memory.
Eight channel interleaving (per socket) - NPS1
•
This interleaves eight channels in a socket.
NOTE:
{CS A, B, C, D} and {CS E, F, G, H} is only recommended as a memory population if all eight channels are
populated as NPS2.
NOTE:
It is recommended that all channels must be populated (CS A, B, C, D, E, F, G, H) for NPS1, but NPS1 does
support a 4 channel configuration of (CS C, D, G, H) but does not have optimal performance.
•
Requires all populated channels in a socket to have equal size memory.
•
Single processor system creates a single NUMA node for the system, the SRAT and SLIT table are not required.
CCX/Last-Level Cache (LLC) as NUMA domains
In addition to selecting the number of NUMA domains via NPS option, the processor allows for making memory per CCX as NUMA
domain. In the processor each CCD has a maximum of two CCXs with each CCX having a shared last-level cache (LLC, or L3 cache) for
all cores. The CCX as NUMA domain option allows for each LLC to be configured as a NUMA domain so that for certain workloads pinning
execution to a single NUMA domain can be done.
The total amount of memory for each default NUMA node is divided by the number of CCXs within each CCD and distributed equally to
each new per-CCX. The max number of NUMA domains generated will based on how many CCD and CCX are fused for that processor
SKU.
62
Installing and removing system components
