Features
Description
8b/10b encoding, it is able to have double the bandwidth of
PCIe Gen2.
The PCIe Gen 3 will be fully compatible with prior generations of
this technology, from software to clocking architecture to
mechanical interfaces.
AHCI
The chipset SATA controller provides hardware support for
Advanced Host Controller Interface (AHCI), a standardized
programming interface for SATA host controllers developed
through a joint industry effort. Platforms supporting AHCI may
take advantage of performance features such as port
independent DMA Engines—each device is treated as a master
—and hardware-assisted native command queuing.
Low Pin Count Interface (LPC)
The chipset implements an LPC interface.
Serial Peripheral Interface (SPI)
The chipset provides one Serial Peripheral Interface (SPI). The
interface implements 3 Chip Select signals (CS#), allowing up to
two flash devices and one TPM device to be connected to the
PCH. The CS0# and CS1# are used for flash devices and CS2#
is dedicated to TPM.
Advanced Programmable Interrupt Controller (APIC)
The I/O APIC within the chipset supports 40 APIC interrupts.
Each interrupt has its own unique vector assigned by software.
Real Time Clock (RTC)
The Real-Time Clock (RTC) performs two key functions—
keeping track of the time of day and storing system data, even
when the system is powered down. The RTC operates on a
32.768-KHz crystal and a 3V battery.
General-Purpose Input/Output (GPIO)
GPIO Serial Expander (GSX) is the capability provided by the
chipset to expand the GPIOs on a platform that needs more
GPIOs than the ones provided by the PCH. The solution requires
external shift register discrete components.
System Management Bus (SMBus 2.0)
The chipset provides a System Management Bus (SMBus) 2.0
host controller as well as an SMBus Slave Interface. The chipset
is also capable of operating in a mode in which it can
communicate with I2C compatible devices. The host SMBus
controller supports up to 100- KHz clock speed.
JTAG Boundary-Scan
This section contains information regarding the chipset
testability signals that provides access to JTAG, run control,
system control, and observation resources. PCH JTAG (TAP)
ports are compatible with the IEEE Standard Test Access Port
and Boundary Scan Architecture 1149.1 and 1149.6 Specification,
as detailed per device in each BSDL file. JTAG Pin definitions are
from IEEE Standard Test Access Port and Boundary-Scan.
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