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                                      LCP-1250RJ3SR-S

 

DELTA ELECTRONICS, INC.

 

  Oct. 17. 2007 Rev. 1.02

 

www.deltaww.com

 

LCP-1250RJ3SR-S EEPROM Serial ID Memory Contents (Two-Wire Address A0h) 

Address 

Hex  ASCII 

Address 

Hex  ASCII 

Address

Hex ASCII

Address

Hex ASCII

Address

Hex  ASCII 

Address 

Hex ASCII

00 03    25 20   

  50 33

3  75 SN

  100 00    125 

00

 

01 04    26 20   

  51 53

S  76 SN

  101 00    126 

00

 

02 00    27 20   

  52 52

R  77 SN

  102 00    127 

00

 

03 00    28 20   

  53 2D

-  78 SN

  103 00   

     

04 00    29 20   

  54 53

S  79 SN

  104 00   

     

05 00    30 20   

  55 20

  80 SN

  105 00   

     

06 08    31 20   

  56 30

0  81 SN

  106 00   

     

07 00    32 20   

  57 30

0  82 SN

  107 00   

     

08 00    33 20   

  58 30

0  83 SN

  108 00   

     

09 00    34 20   

  59 30

0  84 DC Note 

3

109 00   

     

10 00    35 20   

  60 00

  85 DC

  110 00   

     

11 01    36 00    61 00

  86 DC

  111 00   

     

12 0D    37 00    62 00

  87 DC

  112 00   

     

13 00    38 00    63 CS1 Note 

1

88 DC

  113 00   

     

14 00    39 00    64 00

  89 DC

  114 00   

     

15 00   

40 4C L  65 01

 

90 DC

  115 00   

     

16 00    41 43 C  66 00

  91 DC

  116 00   

     

17 00    42 50 P  67 00

  92 00

  117 00   

     

18 64    43 2D -  68 SN Note 

2

93 00

  118 00   

     

19 00    44 31 1  69 SN

  94 00

  119 00   

     

20 44 D  45 32 2  70 SN

  95 CS2 Note 

4

120 00   

     

21 45 E  46 35 5  71 SN

  96 00

  121 00   

     

22 4C L  47 30 0  72 SN

  97 00

  122 00   

     

23 54 T  48 52 R  73 SN

  98 00

  123 00   

     

24 41 A  49 4A J  74 SN

  99 00

  124 00   

     

Notes: 

1)  Byte 63(CS1): Check sum of bytes 0-62. 

2)  Byte 68-83 (SN): Serial number. 

3)  Byte 84-91 (DC): Date code. 

4) 

Byte 95 (CS2): Check sum of bytes 64-94.

 

5)  Byte 128-255 had been set hex.00. 

 

LCP-1250RJ3SR-S Internal PHY Register (Two-Wire Address 0xAC) 

LCP-1250RJ3SR-S is internally designed of physical layer IC (Marvell 88E1111), which can be programmed 

via two-wire interface with the device address 

0xAC

. For details of PHY IC registers in 88E1111, see 

Marvell document 

Alaska Ultra 88E1111 Integrated Gigabit Ethernet Transceiver”. 

Electromagnetic Emission 

FCC Class A, CE Class A, VCCI Class A, C-Tick

 

Summary of Contents for LCP-1250RJ3SR-S

Page 1: ...wire interface The SGMII interface without clock is selected by setting HWCFG_MODE 3 0 bits to 1100 or 1000 Features Compliant with specifications for IEEE 802 3z Gigabit Ethernet Compliant with MSA specifications for Small Form Factor Pluggable SFP Ports Hot pluggable SFP footprint 10 100 1000 BASE T operation in the host system with SGMII interface Default 1000 BASE T operation in the host syste...

Page 2: ...Base T with SGMII interface by reconfiguration of the PHY within the SFP 3 This part supports the 10 100 1000 Base T with SGMII interface by default It can operate in 1000 Base T with SerDes interface by reconfiguration of the PHY within the SFP Serial Interface Configuration PHY Two Wire Address 0xAC Register Bits Field Mode Description 27 3 0 HWCFG_ MODE R W Changes to these bits are disruptive ...

Page 3: ...itter Disable Input High VDISH 2 0 VCC 0 3 V Transmitter Disable Input Low VDISL 0 0 8 V Receiver Data Output Differential Voltage VD RX 0 35 2 V 3 Differential Output Impedance ZRX 80 100 120 Ohm Data Output Rise Fall Time tr Rx tf Rx 180 ps 4 Notes 1 Internally AC coupled and terminated to 100 Ohm differential load 2 Pull up to VCC with a 4 7K 10K Ohm resistor on host Board 3 Internally AC coupl...

Page 4: ...ace 6 MOD DEF0 Module Definition 0 3 Note 3 grounded in module 7 Rate Select Not Connect 3 Function not available 8 LOS Loss of Signal 3 Note 4 Function not available 9 VeeR Receiver Ground 1 Note 5 10 VeeR Receiver Ground 1 Note 5 11 VeeR Receiver Ground 1 Note 5 12 RD Inverse Received Data Out 3 Note 6 13 RD Received Data Out 3 Note 6 14 VeeR Receiver Ground 1 Note 5 15 VccR Receiver Power 2 Not...

Page 5: ...e two wire serial interface respectively 4 LOS Loss of Signal is not supported and tied to ground 5 VeeR and VeeT are internally connected within the copper SFP 6 RD and RD are the received differential outputs and they are AC coupled 100Ω differential lines that should be terminated with 100Ω differential at user s SERDES The AC coupling is done inside the copper SFP and thus not required on the ...

Page 6: ...LCP 1250RJ3SR S DELTA ELECTRONICS INC 6 Oct 17 2007 Rev 1 02 www deltaww com Recommend Circuit Schematic ...

Page 7: ...LCP 1250RJ3SR S DELTA ELECTRONICS INC 7 Oct 17 2007 Rev 1 02 www deltaww com Package Outline Drawing for Metal Housing ...

Page 8: ...0 64 00 89 DC 114 00 15 00 40 4C L 65 01 90 DC 115 00 16 00 41 43 C 66 00 91 DC 116 00 17 00 42 50 P 67 00 92 00 117 00 18 64 43 2D 68 SN Note 2 93 00 118 00 19 00 44 31 1 69 SN 94 00 119 00 20 44 D 45 32 2 70 SN 95 CS2 Note 4 120 00 21 45 E 46 35 5 71 SN 96 00 121 00 22 4C L 47 30 0 72 SN 97 00 122 00 23 54 T 48 52 R 73 SN 98 00 123 00 24 41 A 49 4A J 74 SN 99 00 124 00 Notes 1 Byte 63 CS1 Check ...

Page 9: ...SR GBIC Transceiver 1250Mb s data link up to 100 m on standard CAT 5 UTP References 1 Small Form factor Pluggable SFP Transceiver MultiSource Agreement MSA September 14 2000 2 IEEE Std 802 3 2002 Edition IEEE Standards Department 2002 3 AT24C01A 02 04 08 16 2 Wire Serial CMOS EEPROM Atmel Corporation www atmel com 4 Alaska Ultra 88E1111 Integrated 10 100 1000 Gigabit Ethernet Transceiver Marvell C...

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