69
DVD-3910
Pin Descriptions
Input Pins
Pin Name
Pin #
Type
Description
D23-D12
See Pin
Diagram
In
Upper 12 bits of 24-bit pixel bus. Mode controlled by configuration register bit:
When BSEL = HIGH, this bus inputs the top half of the 24-bit pixel bus.
When BSEL = LOW, these bits are not used to input pixel data.
D11–D0
See Pin
Diagram
In
Bottom half of 24-bit pixel bus / 12-bit pixel bus input. Mode controlled by
configuration register bit:
When BSEL = HIGH, this bus inputs the bottom half of the 24-bit pixel bus.
When BSEL = LOW, this bus inputs ½ a pixel (12-bits) at every latch edge (both
falling and/or rising) of the clock.
IDCK+
57
In
Input Data Clock +. This clock is used for all input modes.
IDCK-
56
In
Input Data Clock –. This clock is only used in 12-bit mode when dual edge
clocking is turned off (DSEL = LOW). It is used to provide the ODD latching edges
for multi-phased clocking. If (BSEL = HIGH) or (DSEL = HIGH) this pin is unused
and should be tied to GND.
DE
2
In
Data enable. This signal is high when input pixel data is valid to the transmitter
and low otherwise.
HSYNC
4
In
Horizontal Sync input control signal.
VSYNC
5
In
Vertical Sync input control signal.
Input Voltage Reference Pin
Pin Name
Pin #
Type
Description
VREF
3
Analog
In
Must be tied to 3.3V.
Power Management Pin
Description
In
Power Down (active LOW). A HIGH level (3.3V) indicates normal operation and a
LOW level (GND) indicates power down mode.
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