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3
BIOS Setup
PCI Delay Transaction
When enabled, this function frees up the PCI bus for other PCI
masters during the PCI-to-ISA transactions. This allows PCI and ISA
buses to be used more efficiently and prevents degradation of
performance on the PCI bus when ISA accesses are made.
3.1.3.4 Memory Hole
This field is used to select the memory area that must not be
addressed to the ISA bus.
3.1.3.5 VLink Data Rate
8x
The speed of VLink which links the North Bridge and South
Bridge is 8x.
4x
The speed of VLink which links the North Bridge and South
Bridge is 4x.
3.1.3.6 Init Display First
This field is used to select whether to initialize the AGP, onboard
VGA or PCI first when the system boots.
AGP
When the system boots, it will first initialize the AGP.
Onboard
When the system boots, it will first initialize the
onboard VGA.
PCI Slot
When the system boots, it will first initialize PCI.
3.1.3.7 System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM ad-
dressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
