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BIOS Setup
Phoenix - AwardBIOS CMOS Setup Utility
LDT & PCI Bus Control
Item Help
Menu Level
X
LDT Configuration
Upstream LDT Bus Width
Downstream LDT Bus Width
LDT/FSB Frequency Ratio
PCIE Reset Delay
Enabled
16 bit
16 bit
Auto
Disabled
↑↓→←
: Move
Enter: Select
F1: General Help
+/-/PU/PD: Value
F10: Save
ESC: Exit
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
The settings on the screen are for reference only. Your version may not be
identical to this one.
LDT & PCI Bus Control
Move the cursor to the South Configuration field and press <Enter>.
The following screen will appear.
LDT Configuration
Set this field to Enabled to configure LDT.
Upstream LDT Bus Width
This field is used to select the utilized upstream data width of the
HyperTransport link.
Downstream LDT Bus Width
This field is used to select the utilized downstream data width of the
HyperTransport link.
LDT/FSB Frequency Ratio
This field is used to select the maximum bus frequency of the link’s
transmitter clock.
PCIE Reset Delay
This field is used to enable or disable the reset delay of the PCI
Express slot.
Summary of Contents for LanParty UT CFX3200-DR
Page 1: ...System Board User s Manual 935 CF3291 000G 90800601 ...
Page 23: ...23 1 Introduction ...
Page 24: ...24 Introduction 1 ...
Page 25: ...25 2 Hardware Installation System Board Layout Chapter 2 Hardware Installation ...
Page 143: ...143 4 Supported Software 4 Click Finish 5 Reboot the system for the driver to take effect ...
Page 146: ...146 4 Supported Software 7 Click Finish 8 Reboot the system for the driver to take effect ...