DG USB3D-IP Manual Download

Page: 16 / 16

dg_usb3.0_dev_ip_demo_instruction_en.doc

15 May 2015

Page 16

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Revision History

Revision

Date

Description

1.0

18-Jul-2012

Release English version.

1.1E

04-Mar-2015

Merged both Altera and Xilinx into one document

1.2E

09-Mar-2015

Updated Figure-15 by the latest test result

1.3E

15-May-2015

Add board support

Summary of Contents for USB3D-IP

Page 1: ...For Altera USB3 0 Device IP evaluation user must arrange following environment Altera evaluation board Cyclone IV GX board in this example USB3 0 adapter board from DesignGateway Part AB08 USB3HSMC USB3 0 A to A cable attached with adapter board Altera sof file download tool programmer and NiosII console Host PC with USB3 0 port PCIe extension USB3 0 host card is also available however such PCIe e...

Page 2: ...on USB3 0 host card is also available however such PCIe extension host card is sensitive to analog characteristics such as error occurrence at some PCIe slot position And PCIe extension host card cannot provide enough transfer performance when PCIe interface is 1 lane and not GEN2 but GEN1 speed because GEN1 1 lane PCIe I F limits its performance to 2 5Gbps 200Mbyte s at maximum Figure Figure Figu...

Page 3: ...CycloneIV GX board J10 for CycloneVE board J14 for ArriaV GX starter board for JTAG programming and JTAG UART operation Set HSMC interface voltage of CycloneIV GX board to 2 5V Short J3 header Refer to CycloneIV GX board manual for more detail Connect adapter board AB08 USB3HSMC to HSMC connector Confirm that JP1 on the adapter board is not jumped OFF Connect USB3 0 AtoA cable with USB connector o...

Page 4: ...nection to CycloneVE board Adapter board connection to CycloneVE board Adapter board connection to CycloneVE board Figure Figure Figure Figure 5 5 5 5 Adapter board connection to ArriaV GX starter board Adapter board connection to ArriaV GX starter board Adapter board connection to ArriaV GX starter board Adapter board connection to ArriaV GX starter board ...

Page 5: ...l from ALTERA NIOS2 Command Shell as below Figure 6 Figure Figure Figure Figure 6 6 6 6 start nios2 start nios2 start nios2 start nios2 terminal terminal terminal terminal When JTAG UART starts its operation it shows message as Figure 7 If nios2 terminal cannot start or this message is not appeared check USB cable or download settings of Programmer Figure Figure Figure Figure 7 7 7 7 Device operat...

Page 6: ...SB3 0 Mass Storage Class operation is started successfully LED2 OFF Cannot initialize USB3 0 LINK process Check HSMC connection of the demo board Check that USB3 0 cable is the demo board attached cable ON USB3 0 LINK initialization completed successfully LED3 OFF USB3 0 Mass Storage Class detection by HostPC is not completed It is possible that signal quality problem exists in the host USB3 0 ada...

Page 7: ...tarts at least following Figure 9 message will appear on the serial console Figure Figure Figure Figure 9 9 9 9 Mass Storage Class operation start message Mass Storage Class operation start message Mass Storage Class operation start message Mass Storage Class operation start message ...

Page 8: ... connector on Xilinx board U29 for KC705 U30 for ZC706 for JTAG programming Connect USB mini cable 2 to USB mini connector on Xilinx board J23 for SP605 J21 for ML605 J6 for KC705 J21 for ZC706 for serial console I F on HostPC Confirm that FMC interface voltage is 2 5V and then connect adapter board AB07 USB3FMC to the FMC LPC connector on Xilinx board Confirm that JP1 on the adapter board is not ...

Page 9: ...er board connection to ML605 Adapter board connection to ML605 Adapter board connection to ML605 Adapter board connection to ML605 Figure Figure Figure Figure 12 12 12 12 Adapter board connection to KC705 Adapter board connection to KC705 Adapter board connection to KC705 Adapter board connection to KC705 ...

Page 10: ...and download evaluation bit file to FPGA b For ZC706 board only set SW11 00000 to configure PS from JTAG and set SW4 01 to connect JTAG to USB to JTAG interface as shown in Figure 14 and Figure 15 After that open ISE command prompt and run bat file to download bit file and elf file to FPGA as shown in Figure 16 Figure Figure Figure Figure 14 14 14 14 SW11 setting on ZC706 board SW11 setting on ZC7...

Page 11: ...Storage Class operation is not started yet SP 605 board might have problem such as memory initialization fail ON USB3 0 Mass Storage Class operation is started successfully DS5 LED2 C OFF Cannot initialize USB3 0 LINK process Check FMC connection of the demo board Check that USB3 0 cable is the demo board attached cable ON USB3 0 LINK initialization completed successfully DS6 LED3 L OFF USB3 0 Mas...

Page 12: ...re Figure Figure 18 18 18 18 Device operation start message Device operation start message Device operation start message Device operation start message When communication with HostPC is successfully started following Figure 19 message will appear on the serial console same meaning of DS6 Figure Figure Figure Figure 19 19 19 19 Mass Storage Class operation start message Mass Storage Class operatio...

Page 13: ...C will firstly request format after power cycle of demo design So user must execute normal format operation If Windows does not show message then execute format manually however in this case enough care must be taken not to format incorrect drive DesignGateway is not responsible for any trouble or problem caused by such incorrect operation DesignGateway is not responsible for any trouble or proble...

Page 14: ...Storage USB Device detected from Device Manager Mass Storage USB Device detected from Device Manager Mass Storage USB Device detected from Device Manager Mass Storage USB Device detected from Device Manager 3 Copy Paste User can execute file or folder Copy Paste to the demo drive for example Note that drive capacity is limited to 127Mbytes only Figure Figure Figure Figure 22 22 22 22 Copy Paster C...

Page 15: ...OS type on the HostPC CPU performance and or PCIe bus speed of the USB3 0 adapter card Figure Figure Figure Figure 23 23 23 23 Benchmark test result example Benchmark test result example Benchmark test result example Benchmark test result example 5 Plug out and Plug in The demo drive can execute plug out and plug in operation as a removable disk Take enough intervals between plug out and plug in f...

Page 16: ...ory Revision History Revision History Revision Date Description 1 0 18 Jul 2012 Release English version 1 1E 04 Mar 2015 Merged both Altera and Xilinx into one document 1 2E 09 Mar 2015 Updated Figure 15 by the latest test result 1 3E 15 May 2015 Add board support Copyright 2012 Design Gateway Co Ltd ...

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