UM-B-114
DA14531 Development Kit Pro Hardware User Manual
User Manual
Revision 1.4
23-Apr-2020
20 of 82
© 2021 Dialog Semiconductor
Figure 14: USB to JTAG (U4)
4.2.4
Voltage Translator
●
Voltage translation is applied to the UART and JTAG signals. The voltage translation is from 3.3
V to V
DDIO
and vice versa.
●
V
DDIO
is generated from U1A, where V3 (V
BAT_HIGH
) is used as a reference. Consequently, there is
no additional power consumption on the power circuitry of DA14531 PRO-MB due to voltage
translation.
Figure 15: Voltage Translator Circuitry of DA14531 PRO-MB
R8
150
R12
10.0k
TP1
VDD_CR
C6
100nF
R11
10.0k
LP2
500m
A_470
OH
M
VBUS_HUB
R14
150
R10
10.0k
C18
18pF
C7
100nF
C8
100nF
TP3
C16 10nF
C17
18pF
TP9
DBLED
C9
100nF
R13
100.0K
C10
100nF
TP8
C11
100nF
R19
39
C14
10uF
R21
6.8k
C19
10pF
C12
100nF
R20
39
C15
10uF
TP6
C13
100nF
J7
TagConnect
1
2
3
4
5
6
TP7
TP10
TP5
TFBGA-100
ATSAM3U2CA-CU
U4
XIN
A2
XOUT
A3
XIN32
A10
NRST
B7
XOUT32
B10
TMS/SWDIO
C7
NRSTB
C8
JTAGSEL
C9
TST
D7
FWUP
D8
TCK/SWCLK
A7
TDO/TRACESWO
B8
TDI
B9
ERASE
D6
VBG
A1
DFSDP
C1
DHSDP
C2
VD
D
BU
C
10
DFSDM
D1
DHSDM
D2
VD
D
PLL
D3
VD
D
C
OR
E1
D4
VD
D
IO3
E6
VD
D
C
OR
E2
E7
VD
D
IO1
F3
VD
D
IO2
F5
VD
D
C
OR
E4
F9
VD
D
C
OR
E5
G5
VD
D
C
OR
E6
H1
AD
VR
EF
J3
VD
D
AN
A
K2
AD
12BVR
EF
K4
PB17
A4
PB21
A5
PB23
A6
VD
D
IN
A8
VD
D
OU
T
A9
VD
D
C
OR
E3
B1
GN
D
U
T
M
I
B2
VD
D
U
T
M
I
B3
PB10
B4
PB18
B5
PB24
B6
GN
D
PLL
C3
PB14
C4
PB19
C5
PB22
C6
PB20
D5
PA11/PGMD3/URXD
D9
PA12/PGMD4/UTXD
D10
PA29
E1
GN
D
2
E2
PA28
E3
PB9
E4
GN
D
BU
E5
PA10/PGMD2
E8
PA9/PGMD1
E9
PA8/PGMD0
E10
PB1
F1
PB12
F2
PA31
F4
GN
D
1
F6
PB16
F7
PA6/PGMM2
F8
PA7/PGMM3
F10
PB11
G1
PB2
G2
PB0
G3
PB13
G4
GN
D
3
G6
PB15
G7
PA3/PGMNVALID
G8
PA5/PGMM1
G9
PA4/PGMM0
G10
PB5
H2
PA27
H3
PA22/PGMD14
H4
PA13/PGMD5
H5
PA15/PGMD7
H6
PA18/PGMD10
H7
PA24
H8
PA1/PGMRDY
H9
PA2/PGMNOE
H10
PB6
J1
PB8
J2
PA30
J4
PB3
J5
PA16/PGMD8
J6
PA19/PGMD11
J7
PA21/PGMD13
J8
PA26
J9
PA0/PGMNCMD
J10
PB7
K1
GN
D
AN
A
K3
PB4
K5
PA14/PGMD6
K6
PA17/PGMD9
K7
PA20/PGMD12
K8
PA23/PGMD15
K9
PA25
K10
VDD_3V3_PERF
VDD_CORE
VDD_3V3_PERF
VDD_3V3_PERF
VDD_CORE
VDD_CORE
VDD_3V3_PERF
VDD_3V3_PERF
TP4
XOUT
USB_DP
PA15
PA18
VDD_3V3_PERF
DFSDM
PA22
DFSDP
VBG
TDIin
PA29
PA4
To VDDBU
NRSTB
FWUP
TCK/SWCLK
TRSTout
TRSTin
PA17
TDIout
TRSTout
TRSTin
Needed for Segger software
NRST
TDIout
TDIin
NRST
TDI
For programming SAM3U2C
ERASE
XIN
SWO/TDO
A_D4_2
NRST
TP76
SWDIO
TP77
SWCLK
D2
Led_Green
2
1
R18
330
TMS/SWDIO
T_SWCLK
T_SWDIO
T_RESET
R9
150
USBDP_1
USBDM_1
Y 1
12.0000MHZ
R16
150
R17
100
R15
100