Hercules-EBX CPU User Manual V1.02
Page 112
appropriate signal can be driven into test point TP1 – pin 4. This test point can be
used for “GATE1” probing and assertion.
•
Channel E, bit 5 is wired to an LED on-board, as well as to SW1 – switch 2. To
loopback DIO E bit 5 to DIO C/D bit 5, set SW1-switch 2 to the “ON” position. To
test “TOUT1” functionality for DIO E – bit 5, either set both DIO D and C to input or
set SW1 – switch 2 to the “OFF” position. DIO E bit 5 can be manually measured at
TP1 – pin 6.
•
Channel E, bit 6 (which is also used for “LATCH” signal functionality) can be
independently connected to DIO channel C / D bit 6 (for DIO loopback testing) or the
“ACK” output signal (for “LATCH” functional testing). Test point TP1 – pin 7 can be
used for “DIO E bit 6 / LATCH” probing and assertion.
i. For loopback testing, SW1 – switch 3 should be set “ON” and SW1-switch
4 should be set “OFF”.
ii. For LATCH / ACK testing, SW1 – switch 4 should be set “ON” and SW1-
switch 3 should be set “OFF”.
•
Channel E, bit 7 can also be used for the “GATE0” function. It can be connected to
DIO Channel C and D bit 4 by selecting SW1 – switch 5 to the “ON” position. In this
configuration, it is directly wired for DIO loop back to Channel C bit 7 and Channel D
bit 7. Test point TP1 – pin 8 can be used for “GATE0” probing and assertion.
In general, DIO loop back requires that one port be set up as an output and the other two ports
should be set as an input. While there is some protection for the case of two or more outputs, this
should not be done and serves no useful purpose in testing.
20.2.3 SPECIAL FUNCTIONS
As has been mentioned previously, Channel E can be used for alternative functions for the DIO
interface. In addition, there are several dedicated signals for some of these special functions.
(See the section 95 for more details).
•
GATE 0 – This signal is used to enable the internal counter 0 of the FPGA, when in
“gated mode”. A high input enables counting and a low input disables counting. This
signal is multiplexed with Channel E bit 7, which means that this input is tied directly
to Channel D bit 7 and channel C bit 7 when SW1 – switch 5 is “ON”. To test this
special function input, either one of these DIO channels (C or D) must be set as an
output and bit 7 of the output channel must be used to control this gating function.
Alternatively, an external source can be used. In this case, SW1 – switch 5 should
be set to “OFF” and an external gating signal should be driven in to TP1 – pin 8.
•
GATE 1 - This signal is used to enable the internal counter 1 of the FPGA, when in
“gated mode”. A high input enables counting and a low input disables counting. This
signal is multiplexed with Channel E bit 4, which means that this input is tied directly
to Channel D bit 4 and channel C bit 4 when SW1 – switch 1 is “ON”. To test this
special function input, either one of these DIO channels (C or D) must be set as an
output and bit 4 of the output channel must be used to control this gating function.
Alternatively, an external source can be used. In this case, SW1 – switch 1 should
be set to “OFF” and an external gating signal should be driven in to TP1 – pin 5.
•
TOUT0 – This signal is used as a timer out from the FPGA timer 0 control. It is a
dedicated output, and is tied to an LED and a test point (TP1 – pin 12) for probing.
•
TOUT1 - This signal is used as a timer out from the FPGA timer 1 control. It is
multiplexed with Channel E bit 5, and is wired directly to Channel D bit 5 and
