Hercules-EBX CPU User Manual V1.02
Page 64
Base + 4
Write
A/D Input Range Control Register
Bit
No.
7 6 5 4 3 2 1 0
Name
LDAD
G1
G0
LDAD
The FPGA contains a global input range setting as well as a 32x4 table for all 32
input channels that can be used for individual input ranges for each channel. The
chip will use either the global input range setting or the individual range table based
on the setting of the SINGLE bit in Base + 12.
If this bit is 1, the remaining bits are stored as the individual input range for the A/D
channel currently set by L4-L0 in Base + 2. If this bit is 0, the remaining bits are the
global setting for all input channels.
G1-0
Gain setting: 0 = gain of 1, 1 = gain of 2, 2 = gain of 4, 3 = gain of 8.
The gain is the ratio between the input voltage and the voltage seen by the A/D
converter. The A/D always works with a maximum input voltage of 10V. A gain of 2
means the maximum input voltage at the connector pin is 5V.
Base + 4
Read
A/D Range/Status Readback Register
Bit
No.
7 6 5 4 3 2 1 0
Name
ADBUSY WAIT DABUSY DABU SEDIFF ADBU G1
G0
ADBUSY 1 = A/D is performing an A/D conversion; 0 = A/D is idle and data may be read out
WAIT
1 = A/D circuit is settling on a new channel or gain setting; program must not initiate
an A/D conversion when WAIT = 1
0 = A/D circuit is ready to perform an A/D conversion
DABUSY 1 = D/A circuit is transferring data to the D/A chip after writing data to the board
0 = D/A circuit is idle / D/A output is stable
DABU
0 = bipolar, 1 = unipolar D/A output range
SEDIFF
0 = single-ended, 1 = differential A/D mode
ADBU
0 = bipolar, 1 = unipolar A/D input range
G1-0
Readback of global A/D gain setting; individual A/D gain settings may not be read
back
