Hercules-EBX CPU User Manual V1.02
Page 71
Base + 28
Read/Write
Watchdog Timer A LSB Data Register
Bit
No.
7 6 5 4 3 2 1 0
Name
WDA7 WDA6 WDA5 WDA4 WDA3 WDA2 WDA1 WDA0
WDA7-0
LSB of timer A divisor; loading occurs for both bytes when the MSB is written
Base + 29
Read/Write
Watchdog Timer A MSB Data Register
Bit
No.
7 6 5 4 3 2 1 0
Name WDA15 WDA14 WDA13 WDA12 WDA311 WDA10 WD9
WD80
WDA15-8 MSB of timer A divisor; loading occurs for both bytes when the MSB is written
Base + 30
Read/Write
Watchdog Timer B Data Register
Bit
No.
7 6 5 4 3 2 1 0
Name
WDB7 WDB6 WDB5 WDB4 WDB3 WDB2 WDB1 WDB0
WDB7-0
Watchdog timer B data register; loading occurs immediately upon writing to this
register.
Base + 31
Read/Write
Watchdog Timer Configuration Register
Bit
No.
7 6 5 4 3 2 1 0
Name WDTRIG
WDEN WDSMI WDRST WDT-1 WDEDGE WDIEN
WDTRIG
If this bit is 1, the remaining bits of this register are ignored and instead the watchdog
timer A is retriggered, i.e. reloaded with its initial value. If this bit is 0, the remaining
bits in this register are used to configure the watchdog timer circuit.
WDEN
Enable watchdog timer circuit: 0 = disabled, 1 = enabled
WDSMI
Enable SMI interrupt upon watchdog timer timeout
WDRST
Enable system reset upon watchdog timer timeout (setting this clears WDSMI)
WDT-1
Enable output pulse from timer A 1 clock early on WDO pin of I/O connectors. This
allows WDO to be connected to WDI to prevent watchdog timer timeout as long as
the timer is running.
WDEDGE Select active edge for hardware (external) retrigger: 0 = rising edge, 1 = falling edge
WDIEN
Enable external input hardware watchdog trigger instead of on-board software trigger:
0 = internal trigger only, 1 = external trigger plus internal trigger are enabled
