Diamond Systems HERCULES-EBX HRC400-5A128 User Manual Download

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Hercules-EBX CPU User Manual V1.02

Page 84

12.3 A/D Scan, Interrupt, and FIFO Operation

The control bits SCANEN (scan enable) and AINTE (A/D interrupt enable) in conjunction with the
FIFO determine the behavior of the board during A/D conversions and interrupts.

At the end of an A/D conversion, the 16-bit A/D data is latched into the 8-bit FIFO in an
interleaved fashion, first LSB, and then MSB. A/D Data is read out of the FIFO with 1 16-bit or 2
8-bit read operations, first Base + 0 (LSB) and then Base + 1 (MSB).

When SCANEN = 1, each time an A/D trigger occurs, the board will perform an A/D conversion
on all channels in the channel range programmed in the A/D Low Channel Register (Base + 2)
and A/D High Channel Register (Base + 3). When SCANEN = 0, each time an A/D trigger
occurs, the board will perform a single A/D conversion and then advance to the next channel and
wait for the next trigger.

During interrupt operation (AINTE = 1), the FIFO will fill up with data until it reaches the threshold
programmed in the FIFO threshold register, and then the interrupt request will occur. If AINTE =
0, the FIFO threshold is ignored and the FIFO continues to fill up.

The FIFO Threshold Registers should be set to the desired depth before configuring the system
to begin operation in interrupt mode. The maximum FIFO depth can be read from the FIFO Depth
ID Register (Page 2: Base + 25): This register should always return a value of a value of “001” for
the FIFO ID: means a maximum depth of 2048 samples.

To set the FIFO depth, the FIFO Threshold should be configured by writing the depth (in samples)
to the “FIFO Threshold Register LSB” (Page 0: Base + 8) and “FIFO Threshold Register MSB”
(Page 0: Base + 9). Note that this setting is in units of “samples”, where one “sample” is 2 bytes.
The current maximum setting would be 2047 (Base + 8 = Hex FF; Base + 9 = 0x07).

If the FIFO reaches its limit (as set in the two FIFO Threshold Registers located at Page 0: Base
+8 and Base +9), then the next time an A/D conversion occurs the FIFO Threshold flag (Base +
14 : bit 3) would be set. At the same time, an interrupt would be generated (if FIFOEN = 1 and
ADINTE = 1).

If the FIFO overflows, then the Overflow flag OVF will be set as the 2049

sample is taken. In this

case the FIFO will not accept any more data, and its contents will be preserved and may be read
out. In order to clear the overflow condition, the program must reset the FIFO by writing to the
FIFORST bit in Base + 15, or a hardware reset must occur.

Note that the current FIFO state can be read at any time by checking the two FIFO Depth
Registers: “FIFO Depth Register LSB” at Page 0: Base + 10 and “FIFO Depth Register MSB” at
Page 0: Base + 11. These registers will return the number of samples currently in the FIFO.
They are incremented with each A/D converter sample stored and are decremented with every
FIFO sample read out (via the A/D LSB Register and A/D MSB register located at Base+0 and
Base + 1, respectively).

In Scan mode (SCANEN = 1), the FIFO threshold should be set to a number at least equal to the
scan size and in all cases equal to an integral number of scans. For example if the scan size is 8
channels, the FIFO threshold could be set to 8, 16, 24, 32, 40, 48, etc. but not less than 8. This
way the interrupt will occur at the end of the scan, and the interrupt routine can read in a complete
scan or set of scans each time it runs.

In non-scan mode (SCANEN = 0), the FIFO threshold should be set to a level that minimizes the
interrupt rate but leaves enough time for the interrupt routine to respond before the next A/D
conversion occurs. Remember that no data is available until the interrupt occurs, so if the rate is
slow the delay to receive A/D data may be long. Therefore for slow sample rates the FIFO
threshold should be small. If the sample rate is high, the FIFO threshold should be high to reduce
the interrupt rate. However remember that the remaining space in the FIFO determines the time
the interrupt routine has to respond to the interrupt request. If the FIFO threshold is too high, the
FIFO may overflow before the interrupt routine responds. A good rule of thumb is to limit the
interrupt rate to no more than 1,000-2,000 per second in Windows and Linux or 10,000 per
second in DOS. Experimentation may be necessary to determine the optimum FIFO threshold for
each application.