Digital Electronics Corporation VT240 Series, Technical Manual

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Page 2: ...EK VT240 TM 001 VT240 Series Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...K VT240 TM 001 VT240 Series Technical Manual Prepared by Educational Services of Digital Equipment Corporation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 4: ...rference will not occur in a particular installation If this equipment does cause interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures reorient the receiving antenna relocate the computer with respect to the receiver move the computer away from the...

Page 5: ...tates Operating Modes VT100 Mode VT200 Mode Seven Bit VT200 Mode Eight Bit VTS2 Mode ReGIS Mode 4010 4014 Mode Controls Controls CONTROLS INDICATORS AND CONNECTORS General System Box VS240 Monochrome Monitor VR201 Color Monitor VR241 Keyboard LK201 Main Keypad Editing Keypad Auxiliary Keypad Top Row Function Keys Visual Indicators Audible Indicators Audible Keyclick Be 11 Connector Cable iii CONTE...

Page 6: ...ontrol Gates Address Latch Decode Memory Map Memory Access Read Only Memory ROM RAM Ra ndom Access Memory I O Buffer I O Decode Keyboard Interface I F 8251A USART Internal Circuits 8251A USART Addresses 8251A USART Timing Diagrams Nonvolatile RAM NVR Interrupt Control Command Register Clock Generator Signal Descriptions Schematic Reference Information SYSTEM COMMUNICATION LOGIC Genera 1 Major Circ...

Page 7: ... 8085A 2 Microprocessor Device Transactions Character Processor CP Memory Video Access Graphics Processor PD7220 Graphics Display Controller GDC Internal Circuits PD7220 Graphics Display Controller GDC Addresses PD7220 Graphics Display Controller GDC Transactions Timing and Control Circuits Clock Generator BEN and STOP Gates ROM Address Counter Timing Signal Generator Read Modify Write RMW Generat...

Page 8: ... Mode Keyboard Receive Mode Reset Signal for 81351 Microprocessor Hardware Keyboard Identification ID Voltage Supplies Keyboard Programming Keyboard Layout and Key Identification Modes Special Considerations Regarding Autorepea t Special Considerations Regarding Down Up Mode Autorepeat Rates Keyboard Peripherals Aud i 0 Indicators LEDs Keyboard to System Module Protocol Keycode Transmission Specia...

Page 9: ...t and Fan Components Power Supply 1 PSI DC Power Input Connector Jl 5 V Input Circuit 12 V Input Circuit 12 V Input Circuit DC Power Okay Circuit INTEGRAL MODEM OPTION General Compatibility and Features Functional Description Physical Description Power Requirements Temperature and Humidity Major Circuits Talk Data Relay Circuit Switch Hook Detector Circuit Ring Detector Circuit Hook Relay Circuit ...

Page 10: ...te Data Loopback Test RDL 10 16 Test Mode Indicate Test IND 10 16 APPENDIX A SPECIFICATIONS APPENDIX B VT240 VT102 DIFFERENCES APPENDIX C VT240 VT125 DIFFERENCES APPENDIX D REGISTER BIT VALUES APPENDIX E VIDEO LOGIC WRITE MODE PROGRAMMING OVERVIEW FIGURES 1 1 1 2 2 1 VT240 Series Video Terminals VT240 Series Terminal Block Diagram System Box Controls Indicators and 1 2 1 2 Connectors 2 1 2 2 2 3 2...

Page 11: ...Terminal System Block Diagram CPU Logic Block Diagram CPU Block Diagram TIl Internal Block Diagram Power Up Sequence TIl Timing Diagram TIl 16 Bit Dynamic Read Transaction Diagram TIl 16 Bit Dynamic Write Transaction Diagram TIl Refresh Transaction Diagram TIl ASPI Transaction Diagram Mode Reg i ster Control Gates Block Diagram Address Latch Block Diagram Memory Map Block Diagram VT240 Series Term...

Page 12: ... Read Write Transactions Character Processor CP Memory Block Diagram Video Access Block Diagram Graphics Processor Block Diagram PD7220 GDC Block Diagram PD7220 GDC Timing Diagram CPU CP Write 6 7 6 8 6 10 6 13 6 13 Transacti on 6 18 PD7220 GDC Timing Diagram CPU CP Read Transaction PD7220 GDC Timing Diagram Display Timing PD7220 GDC Timing Diagram Video Sync Signals PD7220 GDC Timing Diagram 2 Pl...

Page 13: ...3 Example VT240 Series Terminal System Block Diagram Monochrome Monitor Exterior View Monochrome Monitor Block Diagram Monochrome Monitor System Communications Diagram Composite Video Signal Representation Composite Video Sync Timing Diagram Monitor Module Block Diagram Moni tor Modul e Pl Pi nout VT240 Series Terminal System Block Diagram Power Supply Block Diagram AC Input and Fan Components Blo...

Page 14: ...r Upper CTUR and Lower CTLR Registers 2681 DUART Auxiliary Control Register ACR 2681 DUART Interrupt Status Register ISR 2681 DUART Interrupt Mask Register IMR 2681 DUART Output Port Configuration Register OPCR Comm Modem Control Comm Control write CCWR and Read Registers CCRD Comm Modem Control Modem Control write Register MCWR Comm Modem Control Modem Control Read Register MCRD PD7220 GDC Status...

Page 15: ... Circuit I O Addresses PD7220 GDC Commands Summary Video Output Map VOM Addressing Intensity Definition for Output Map Outputs Video Logic Signal Description Video Logic Schematic References Keyboard Matrix Keyboard Functional Divisions Keycode Translation Table Peripheral Commands in Hexidecimal Keyboard Division Default Modes Default Rates in Autorepeat Buffers J1 Pin out J3 Pin out Composite Vi...

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Page 17: ...uction introduces the VT240 Series terminal Chapter 2 all VT240 connectors Controls Indicators and Connectors describes Series terminal controls indicators and Chapter 3 System Overview provides an overview of the VT240 Series terminal system interactions Chapters 4 through 10 identify the major logics that comprise the VT240 Series terminal and identify and describe the major circuits within thos...

Page 18: ...uipment Corporation publications refer to Related Documentation The final part of this provide specifications programming reference data manual is made up of Appendices which differences between terminals and Appendix A Specifications provides VT240 Series terminal specifications Appendix B VT240 VT102 Differences differences between the VT240 Series terminal Appendix C VT240 VT125 Differences dif...

Page 19: ...B VR241 A Series Documentation VT241 A Series Installation Owner s Guide VT241 A Series Installation Guide VT241 A Series Mini Maintenance Manual VT241 A Series Pocket Service Guide Maintenance Print Sets VT240 VS240 VR20l LK201 VS240 System Box VR201 Monochrome Monitor LK201 Keyboard Module VR241 Color Monitor xvii EK VT240 PS EK VT240 RM EK VT240 HR EK VT240 UG EK VT240 IN EK VT24X IN EK VT240 I...

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Page 21: ...ing In addition the terminal also has a 4010 4014 mode to support industry standard Tektronix software packages 1 2 PHYSICAL DESCRIPTION The terminal Figure 1 1 consists of three units a monitor a keyboar and a system box 1 2 1 NOTE Appendix A provides specifications for the VT240 Series terminal System Box VS240 The system box is the center of the terminal Figure 1 2 shows the major system box co...

Page 22: ...minals SYSTEM BOX L KNTEGRAl MaDEJ OPTiON POWER J SUPPLY PS LOGIC BOARD ASSEMBLY MA 1442 83 Figure 1 2 VT240 Series Terminal Block Diagram 1 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 23: ...he VR201 a 12 inch monochrome monitor The VT241 uses the VR241 a 13 inch color monitor 1 3 DISPLAY CAPABILITIES Text and graphic image display is done by raster scan of an 800 X 240 picture element pixel matrix The VT240 Series terminal display capabilities are upward compatable with VT102 text capabilities and with VT125 graphics capabilities In addition VT240 Series terminals contain an operatio...

Page 24: ... and one mode executes Digital private functions VT52 mode The following major text capabilities are available within these various modes 24 rows of text with either 80 or 132 characters per row characters formed within 7 X 9 dot matrix in 10 X 10 cell for 80 characters per row and within 5 X 9 dot matrix in 6 X 10 cell for 132 characters per row 5 character sets of 94 characters each including DE...

Page 25: ... a pixel to pixel basis at a given time VT241 Four monochrome shades displayable on a pixel to pixel basis at a given time VT240 COMMUNICATION ENVIRONMENT The terminal s major communications features include 1 5 Asynchronous communications at up to 19 2K bits per second EIA RS232C host port 20 rnA host port EIA RS232C auxilliary port Seven bit or eight bit character formats Optional integral moder...

Page 26: ... keys that have a direct functional counterpart on the VT102 keyboard All data is restricted to seven bit format and only ASCII U K or special graphics characters are generated 1 6 2 VT200 Mode Seven Bit Controls The VT200 mode with seven bit controls executes standard ANSI functions to provide the full range of VT240 Series terminal capabilities while using seven bit controls in a seven bit or ei...

Page 27: ...K or special graphics characters are generated 1 6 5 ReGIS Mode ReGIS mode is a graphics instruction set available when the terminal is in VT100 mode or either VT200 mode ReGIS provides a full range of graphic image capabilities and has a high degree of compatability with the ReGIS instruction set in Digital s VT125 Appendix C describes the differences between a VT240 and VT125 1 6 6 4010 4014 Mod...

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Page 29: ...the system box on or off EIA Host Port Connector connects the system box to a host computer either directly or via an external modem rz s INTEG RAL MODEM OPTION PANEL AC T CONNECTOR 0 I i FUSE 0 o IQ l t l j VOLTAGE SELECTION 20 rnA HOST PORT POWER OK KEYBOARD SWITCH CONNECTOR INDICATOR CONNECTOR EIA HOST PORT COMPOSITE VIDEO PRINTER PORT CONNECTOR OUTPUT CONNECTOR CONNECTOR POWER SWITCH VIDEO MON...

Page 30: ...T240 or to the connector at the VR24l color monitor end of the system box connection cable for the VT24l AC Input Connector system box connects the power cord to the Fuse protects the system box from electrical damage Voltage Select Switch matches the input voltage selected for the system box to the voltage supplied at the wall outlet CAUTION The wrong voltage select switch setting can cause damag...

Page 31: ...trols Indicators and Connectors Keyboard monitor box Connector The keyboard connects the keyboard to the can also connect to the system Pushbutton releases a post that drops to provide a 30 degree tilt range for adjusting the monitor angle Carry Handle the monitor provides an easy and safe way to carry 2 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 32: ...llowing Power Switch turns the monitor on or off Video Cable Connectors connect the system box to the monitor POWER OK INDICATOR MA_0039_84 Figure 2 3 VR241 Monitor Controls Indicators and Connectors Front and Rear 2 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 33: ...ization source to the monitor Impedence Switch selects 75 ohm or high impedence Voltage Select Switch matches the input voltage selected for the monitor to the voltage supplied at by the wall outlet CAUTION The wrong voltage select switch setting can cause damage to the monitor 2 5 KEYBOARD LK20l The LK201 keyboard Figure 2 4 consists of the following parts Main keypad Editing keypad Auxiliary key...

Page 34: ...t I _ Screen Screen Set Up Talk Break F6 F7 F8 F9 FlO ESC BS IF F14 _ _ _ _ F17 F18 F19 F20 ooooonooooonOOoonBI Do Inoooo DD u uuuu D D DDD D D DLJ D DDDD D IShih 1 EJDD ISh h 1 Dnte 1 I 1 10 Figure 2 4 Keyboard North American Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 35: ...th another key generates either the key s shifted value for alphanumeric and two symbol keys or as with some function keys generates a predefined control function such as SHIFT and x which generates a CANCEL control character RETURN Key generates a carriage return or carriage return and linefeed as selected in set up In some cases RETURN moves the cursor to the next line during text editing or in ...

Page 36: ...plication program in effect 2 5 3 Auxiliary Keypad The auxiliary keypad Figure 2 7 is used primarily to enter numeric data However some keys on this keypad PFl PF2 PF3 and PF4 can have different functions depending upon the application software The ENTER key causes a carriage return or a carriage return and linefeed as selected in set up and is also used in set up mode to activate selected feature...

Page 37: ...t if BREAK generation is enabled in set up SHIFT and BREAK initiates a disconnect while CTRL and BREAK sends the answerback message to the host F11 ESC generates an ESC character in either VT100 or VT52 mode the function is determined by application programs in either VT200 mode F12 BS generates a BS character in either VT100 or VT52 mode the function is determined by application programs in eithe...

Page 38: ...Talk F6 F7 FS F9 FlO ESCI F12 SS F13 IF F14 Hold Screen lock Compose Walt F17 F18 F19 F20 I DDDDDnDDDDDnDDDDnBI Do InDDDD Figure 2 8 Top Row Function Keys and LEDs Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 39: ...n the SHIFT or CTRL keys are depressed because these keys do not generate characters only modify characters generated by other keys When the WAIT indicator is on characters from the keyboard will be lost When the keyclick is disabled in set up When an inactive key is pressed 2 5 6 2 Bell cases The bell tone sounds in each of the following As part of the power up self test When the terminal receive...

Page 40: ...tor for the BCC01 cable 12V IN PIN 3 SERIAL OUT PIN 4 SERIAL IN Pli 1 CABLE CONNECTOR WIRING KEYBOARD END SIGNAL SERIAL IN GROUND 12 V IN SERIAL OUT PIN NO 1 2 3 4 PIN NUMBERS 4 3 2 1 MONITOR END SIGNAL PIN NO SERIAL OUT 4 GND 3 12 V 2 SERIAL IN TOP VIEW OF KEYBOARD JACK SIGNALS ARE REVERSED AT MONITOR MA 0740 84 Figure 2 9 Connector for BCCOl Cable 2 12 Artisan Technology Group Quality Instrument...

Page 41: ...pressing the SET UP key to Examine or change terminal operating characteristics such as transmit and receive speeds Transfer from on line mode to local mode or from local mode to on line mode While in set up mode the terminal is functionally disconnected from the host Only the keyboard is enabled as an input device and only the monitor is enabled for output Any data received from the host is buffe...

Page 42: ...odem Communication is through a direct line link with the host either through the EIA host port or the 20 rnA port External Modem Communication is with a remote host using the external modem linked to the terminal through the EIA host port Integral Modem Communication is with a remote host the terminal is linked to the host through telephone connectors provided by the integral modem option When th...

Page 43: ...al block diagram of the terminal This diagram shows the following major components and or logics CPU logic Video logic System communication logic Integral modem option Power supply Keyboard Monitor SYSTEM BOX VIDEO LOGIC LOGIC __ L _ _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 mA HOST PORT PORT PORT LOGIC BOARD OPTIONAL HOST COMMUNICATIONS MONITOR VR201 OR VR241 MA OO 4 84 Figure 3 1 VT240 Serie...

Page 44: ...4 mode VT52 mode and serial I O handling Video Logic The video logic develops the video output signals necessary to drive the terminal monitor The video logic consists of the following major circuits components 8085 microprocessor and associated circuits used as a character accelerator for high speed writing of text characters into the video logic Video controller to perform DMA direct memory acce...

Page 45: ...al modem consists of the following major circuits components Two four pin telephone jack connectors for interfacing with the telephone line 3 3 5 Handshake circuits to control communication between the terminal and remote host Power Supply The power supply generates the operating voltages required by the system box keyboard and VR201 monochrome monitor the VR241 color monitor has its own power sup...

Page 46: ...rightness and contrast controls The VR241 also contains its own power to the operating voltages required develops its operating voltages from power supply in the system box 3 4 SYSTEM INTERACTION supply to convert ac input by this monitor The VR201 dc voltage provided by the Figures 3 2 through 3 15 provide an overview of the information flow within the terminal for various system configurations d...

Page 47: ...ED FROM THE KEYBOARD TO THE CPU LOGIC 2 IF SCREEN DISPLAY IS TO BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY 3 IF DATA IS TO BE OUTPUT TO AN AUXILIARY DEVICE CPU LOGIC DIRECTS TRANSFER OF DATA AND CONTROLS TO AUXILIARY DEVICE VIA PRINTER PORT PORTION OF SYSTEM INTERFACE LOGIC MA 1445 83 System Interaction in Local Printer Port as Output Port 3 7 Artisan Technology Group Quality Instr...

Page 48: ... TO ALTER DISPLAY MA 144 83 System Interaction in Local Printer Port as Input Port 1 DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC 2 DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST VIA EITHER EIA HOST PORT OR 20 rnA PORT PORTIONS OF THE SYSTEM COMMUNICATION LOGIC 3 IF LOCAL ECHO IS ENABLED AND SCREEN DISPLAY IS TO BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY MA 1447 83 Sy...

Page 49: ... OR THE AUXILIARY DEVICE VIA PRINTER PORT PORTION OF THE SYSTEM COMMUNICATION LOGIC IF DATA IS PRESENT FROM BOTH SOURCES AND BOTH ARE ENABLED CPU LOGIC WILL DETERMINE WHICH DATA TO PROCESS FIRST 2 DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST VIA EITHER EIA HOST PORT OR20 rnA PORT PORTIONS OFTHE SYSTEM COMMUNICATION LOGIC 3 IF LOCAL ECHO IS ENABLED AND SCREEN DISPLAY IS TO BE AFFECTED CPU LOG...

Page 50: ...ICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION LOGIC System Interaction in On Line Printer Port as Output Port MA 1450 83 1 DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE HOST VIA EITHER EIA HOST PORT OR 20 mA PORT PORTIONS OF THE SYSTEM COMMUNICATION LOGIC 2 DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE AUXILIARY 1 0 DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION LOGIC Syste...

Page 51: ...EO LOGIC TO ALTER DISPLAY MA 1452 83 System Interaction in On Line Printer Port as Inactive or Output Port Q V 1 DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST VIA EITHER INTEGRAL MODEM OR EIA HOST PORT PORTIONS OF THE SYSTEM COMMUNICATION LOGIC 2 IF SCREEN DISPLAY IS TO BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY System Interaction in On Line Printer Port as Inactive or Input P...

Page 52: ... BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY MA 1454 83 System Interaction in On Line Printer Port as Input Port Q V 1 DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST VIA EITHER INTEGRAL MODEM OR EIA HOST PORT PORTIONS OF THE SYSTEM COMMUNICATION LOGIC 2 IF SCREEN DISPLAY IS TO BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY 3 IF DATA IS TO BE OUTPUT TO AN AUXILIARY DE...

Page 53: ...OF THE SYSTEM COMMUNICATION LOGIC 2 DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE AUXILIARY I O DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION LOGIC MA 1456 83 System Interaction in On Line Printer Port as I O Port 3 13 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

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Page 55: ...components Directs system communication logic keyboard module operation video logic and Initializes system at power up and executes self test programs SYSTEM BOX Figure 4 1 I I VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 mA HOST PORT PORT PORT INTEGRAL OPTIONAL HOST COMMUNICATIONS MONITOR VR201 OR VR241 MA Q054 84 VT240 Series Terminal System Block Diagram 4 1 Artisan Tech...

Page 56: ...mory ROM Nonvolatile random access memory NVR Volatile random access memory RAM Memory map Interrupt control Command register Clock generator I O buffer I O decode Keyboard interface I F 1 CPU 1 CPU I LOGICI CLOCK INTERRUPTS CONTROLS 1 ___ PART OF SYSTEM COMMUNICATION VIDEO LOGIC _ _ _ _ KYBD DATA ADDRESS MA 0163 84 Figure 4 2 CPU Logic Block Diagram 4 2 Artisan Technology Group Quality Instrument...

Page 57: ...ions desired Initializes the system programming stored in terminal s readiness on ROM power up and executes test memory to determine the FROM CLOCK GENERATOR XTAL 1 Figure 4 3 Tll BCLR All H AI7 H DALO H DAL15 H IN IT I INIT L TO FROM RAM INTR CONTROL TO FROM CPU LOGIC CIRCUITS DRAS L DCAS L TO CPU LOGIC 1 TO SYSTEM PI L CIRCUITS PI H R WLB H R WHB H SEL 0 TO SEL 1 CONTROL 1 GATES MA 0144 84 CPU B...

Page 58: ...a description of the values defined by the external mode register Address Register contains the RAM address to be accessed by the next read or write operation Clock Buffers buffers timing input from clock generator Power Control monitors power conditions by generating a clear signal output for VT240 initialization when sensing a power on condition Refresh Counter defines the RAM address to be acce...

Page 59: ...D RESS INTE RRUPT BUFFERS n AIO H AI7 H 16 BIT INTERNAL BUS IINSTRUCTION REGISTER I I STATUS REGISTERl 1 INTERNAL CONTROL MODE REGISTER I CONTROL IDATA ADDRESS I BUFFERS DCAS L R WLB H DRAS L SELO 1 R WHB H DALO H DAL 15 H MA 0171 84 Figure 4 4 Tll Internal Block Diagram Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 60: ... to execute one micro instruction The microcycle performs all the functions necessary for transferring data internally and externally and for calculating values Each read write refresh and NOP microcycle is contains three clock phases 01 02 and 0W ASPI transactions contain a fourth clock phase phase D 0D which is added between 02 and 0W All clock phases have the same duration between assertions an...

Page 61: ...ST FETCH 89 ts AFTER PUP H AT ADDRESS 000000 4 INIT L 30 ns AFTER BCLR L A MAPPER OFF B 8085 RESETS C KYBD UART RESET LPBK OFF D COMM SEL EIA CONN E HOST PRTR UART RESET DISABLES Tx Rx STOPS CTR TIMER ALL OUTPUTS HI F MODEM OPTION DESELECTED BELL 212A 1200 BAUD DOMESTIC 10 BITS TEST OFF ANSWER AND OFF D HI G NVR RECALL Power Up Sequence 4 7 MA 0135 84 Artisan Technology Group Quality Instrumentati...

Page 62: ...7 ns 501 PI H 1 107 6 nS 234 ns l R WLB X MEM MAP x 68 nsF DRAS L __ 94 9 ns 584 ns DCAS L 1 146 ns 324 5 ns PI L 1 123 ns l 249 ns NOTES 1 RAS PRECHARGE 151 ns 2 MAX RD DATA AVAIL 493 ns 3 CAS H TO DAL 15 0 118 ns MA Q252 84 Figure 4 6 Tll Timing Diagram 4 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 63: ...CAS L CAS L RAS L PI R WHB H R WLB H y ADDRESS STROBES MA 4849 MA 0134 84 Figure 4 7 Tll 16 Bit Dynamic Read Transaction Diagram 4 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 64: ... WHB R WLB RIWHB H RIWLB H Figure 4 8 y J ADDRESS STROBES DATA OUT v DATA STROBES MA 0137 84 TIl 16 Bit Dynamic Write Transaction Diagram 4 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 65: ... 4 9 AI 1 4 RAS L CAS L PI Figure 4 10 REFRESH ADDRESS MA 4865 MA 0136 84 TIl Refresh Transaction Diagram INT REQUEST MA 4863 MA 0138 84 TIl ASPI Transaction Diagram 4 11 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 66: ...ts in response to CPU control and flag signal signals The control gates Figure 4 12 consist of the following two decoding circuits Output Flag Decode Gates decode SEL0 SELl inputs to enable either refresh activity REF H or address strobe activity RRAS L from DRAS L with strobe activity occurring with or without I O decode operation BUSOP L R W Decode Gates decodes CPU read and write control signal...

Page 67: ...AL9 H 0 Dynamic memory DAL10 H 1 4K 16K memory DAL11 H 0 16 bit bus DAL12 H 1 User DAL13 H DAL15 H Octal 5 Start address of 000000 restart 000004 Table 4 2 Output Flag Decode Gates Truth Table Input Values Output Values SEL 0 SEL 1 DRAS L REF H RRAS L BUSOP L 0 0 1 0 1 0 0 0 0 0 0 0 1 0 X 1 1 1 X 1 1 0 1 1 X 1 0 0 0 1 X Don t care 4 13 Artisan Technology Group Quality Instrumentation Guaranteed 88...

Page 68: ...L O h_ _ _ _ _ L y TO RAM DRAS L 1Fc FROM CPU IBUSOP L L f _________ r TO I O DECODE L_______ R WHB H R WLB H PI H PI L TO I O BUFFER TO RAM TO NVR TO I O DECODE TO CMD REG TO MEM MAP I TO SYSTEM COMM TO MEM MAP L _____ 1 TO I O DECODE MA 0159 84 Figure 4 12 Control Gates Block Diagram 4 14 Values WLB L 1 1 1 0 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisan...

Page 69: ...g address from address latch and data from I O buffer inputs to develop values for the most significant 8 bits of the mapped 20 bit address The memory map Figure circuits conponents 4 14 consists of the following Map Input Mux is enabled by MEM MAP CS L true low to pass values of LDA12 H LDA15 H to the inputs of the map adders When MEM MAP CS L is high or false LDAI H through LDA4 H values are mux...

Page 70: ... from the map adders gate for write operation One adds map input mux inputs to RDA0 H RDA3 H inputs from the I O buffer and the other adds map input mux signals against RDA4 H RDA7 H inputs from the I O buffer When a high is present from the map adders gate the adders are enabled to read out the value obtained during the last write operation Memory Map Register is enabled by ORed MEM MAP CS L and ...

Page 71: ...ow inputs both true with the MAP ON H output acting as an input select signal for the map output mux Map Output Mux consist of two mux devices each enabled by MAP ON H high true to pass map adders inputs or when MAP ON H is low false to pass LDA12 H LDA15 H out as MDA12 H MDA 15 H and all low conditions from ground inputs out as MDA16 H MDA19 H Figure 4 15 is an overall address map of the VT240 La...

Page 72: ...ROM can consist of up to six separate ROM devices with a total ROM space of 96K bytes Figure 4 17 ROM 1 CS L MEMORY ROM 2 CS L TO ROM ACCESS ROM 3 CS L DECODER RAM CSL TO RAM MDA15 H MDA19 H MDA18H IS NOT USED FROM I O EN H I O DECODE DRAS L FROM CPU MA 0150 84 Figure 4 16 Memory Access Decode Block Diagram FROM ADDRESS LATCH ROM ROM 1 2 LO LO FROM I MDA12 H MDA14 H j ROM ROM 1 2 HI HI MEMORY MAP ...

Page 73: ...re 4 6 the TIl timing diagram and Figure 4 7 and Figure 4 8 the TIl read write transaction diagrams During refresh transactions only row addressing is required RAM is refreshed after 128 refresh cycles one cycle for each of the 128 rows The RAM circuit Figure 4 18 consists of the following circuits and components RAM CAS Gates consists of nine gates that enable read read word only or write write u...

Page 74: ... high developed from MUX H input to the input mux during refresh transactions The output mux selects A inputs MDA16 H MDA14 H and MDA12 H when RAM MUX H is false low developed from RRAS L input to the input mux during read write transactions RAM Devices consist of 16 MOS 16K bit X 1 RAM devices arrayed in 2 banks of 8 bits One bank is for the most significant byte of memory enabled for read write ...

Page 75: ...DAL 0 DAL 1 DAL 2 DAL 3 DAL 4 DAL 5 DAL 6 DAL 7 GATES RAM H I C A S L lr r r r r FROM Tll R WHB H Figure 4 20 D15 D14 D13 D12 Dll Dl0 D9 NOTE ADDRESS AND RRAS L INPUTS ARE NOT SHOWN RAM Devices Array 4 21 D8 DAL 11 DAL 12 DAL 13 DAL 14 DAL 15 RAM LO CAS L RAM HI CAS L TOI FROM Tll MA 0152 84 TO RAM DEVICES MA 0164 84 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www art...

Page 76: ... by the I O buffer Data is transferred from the RDA lines to the DAL lines only when both IO EN Hand RD H are true both high Data is transferred from the DAL lines to the RDA lines for all other conditions during TIl read write of memory data is transferred by the I O buffer to the RDA lines but has no effect as no I O device is enabled Later in this chapter Table 4 6 describes the signals shown i...

Page 77: ...M MAP CS L MEM MAP SEL L CMD REG RD L TO tMEM JMAP TO CMD REG _ TONVR RD BUF L WR BUF L 8085 RESET L VIDEO MEM MAP L FROM WLB L CONTROL jTO LOGIC WR 8UF L KYBO L GATES TO H O S T P RT R L t c c _ KYBD I F I O ADDRESS LDA9 H LDAll H GRD L DECODER GWRB L 1 G85 L LATCH NVR L TO MODEM L NVR INIT L __ FROM CONTROL W LB L lr L V ID AC C E S S L GATES GWLB L TO DCAS L VIDEO FROM GRD L LOGIC FROM CPU DRAS...

Page 78: ... signal to WLB L Graphics R W Gates consists of the AND gate and two OR gates The AND gate generates a VID ACCESS L low output true whenever either GRD L or GWLB L is low true The OR gates tie GRD L to DCAS L and GWLB L to WLB L Communications Comm R W Gates gates DCAS L with LDAl signals to generate either COMM WR L LDAl signals true or COMM RD L LDAl signals false The RD H input is used to disab...

Page 79: ... 174131313 Video logic VID ACCESS L 173131313 174131313 Video logic G8e85 L 175eex Video logic RD BUF L 175131313 Video logic WR BUF L 17513132 Video logic 81385 RESET L 17513134 Video logic NVR L 176XXX NVR MODEM L 177eex System comm logic x Indicates that a specified select signal can be active for various addresses within the defined range as different functions can be addressed while the speci...

Page 80: ...used for testing The loopback gates are enabled by 825lA output LPBK EN L developed from the DTR output of the 8251A to route transmit tx data back to the 8251A as receive rx data Keyboard Transmit Data KYBD TxD Buffers convert TTL level tx data signals from 8251A into 12 V 12 V level outputs to the keyboard module Keyboard Receive Data KYBD RxD Buffers convert 12 V 12 V rx data signals from the k...

Page 81: ...8251A internal circuits Data Bus Buffer buffers data transfer between the TIl as RDA0 H RDA7 H and registers within the 8251A command status transmit data and receive data register devices Modem Control is used by the TIl to generate the loopback enable LPBK EN L generated by DTR output for IIF testing TxD Buffer converts parallel data input to a tx data register into serial output for the keyboar...

Page 82: ...A operating parameters as well as a status register to report operating conditions to the TIl and circuits required to determine what type of access is being attempted by the TIl The TIl can attempt the following types of access Data read LDA2 H low or false with COMM RD L low or true Data write LDA2 H low or false with COMM WR L low or true Command write LDA2 H high and COMM WR L low both true co...

Page 83: ...ate bytes of programming The first byte written defines the mode instruction format the second byte written defines the command data for that mode format Both bytes are written to the 825lA command register immediately following a power up sequence or following an 8251A internal reset Table 4 5 defines the 825lA internal registers that the TIl can address the register s address the type of operati...

Page 84: ...51A USART Transmit Data TxD Timing Diagram OVERRUN ERROR STATUS BIT KYBD INTR2 L LDA2 H COMM WR L COMM RD L RxD L NOTES KYBD INTR2 L IS SHOWN ENABLED FOR RX READY CONDITION 2 TRxR IS A MAXIMUM OF 8 CLOCK PERIODS 3 COMM RD L IS LOW TRUE FOR READING RX DATA AND COMM WR L IS LOW TRUE FOR WRITING CONTROL FOR RX DATA INPUT 4 LDA 2 H IS SHOWN HIGH TRUE FOR WRITING CONTROL FOR RX DATA INPUT AND LOW FALSE...

Page 85: ...he EPROM effectively reprogramming the EPROM At the next power up sequence the new EPROM values are transferred back into the NVR RAM and these values now determine the terminal s starting parameters The NVR Figure 4 27 consists of the following circuits components NVR Strobe Gates are enabled by NVR STORE L low true and LDA8 H low false to generate a store input to the NVR device The store input ...

Page 86: ...R functionality Read Terminal Operating Parameters RD H is true high DCAS Land NVR L are both low both true and LDAl H LDA8 H define the portion of the NVR device s RAM memory to be affected write Terminal Operational Parameters This is the same as a read transaction except RD H is low false Store RAM Values in EPROM true with LDA8 H low false NVR STORE L is low Transfer EPROM Values to RAM INIT L...

Page 87: ...by PI L low true to output as All H AI4 H the four bit code at the memory location defined by inputs from the interrupt buffer PROD TEST2 L input is always high or false as it is tied to 5 V with this four bit code defining the current interrupt status to the TIl Later in this chapter Table 4 6 describes the signals shown in Figure 4 28 5 FROM VIDEO LOGIC PROD TEST 2 L V 8085 RDY L FROM KEYBOARD 1...

Page 88: ...AS L low true condition and those values read out of the register as RDA0 H RDA7 H whenever a low is input from the command register gate Later in this chapter Table 4 6 describes the signals shown in Figure 4 29 FROM MEM MAP FROM ROM FROM RAM IC FROM KYBD I F FROM VIDEO LOG FROM SYSTEM COMM FROM VIDEO LOG IC F C ROM PU MAP ON H PGM H A7 H LPBKEN L MONITOR PRES L MOD PRES L 8085 RDY L T11 L DCAS L...

Page 89: ...MHZI TOCPU C L K2 H 3 68 64 _ _ TO KYBD IIF TO SYSTEM COMMUNICATION LOGIC MA 016 84 Figure 4 30 Clock Generator Block Diagram 4 3 SIGNAL DESCRIPTIONS Table 4 6 gives descriptions of all the signals identified in this chapter These descriptions are provided for reference and are listed alphabetically by mnemonic numeric mnemonics are listed last 4 4 SCHEMATIC REFERENCE INFORMATION Table 4 7 identif...

Page 90: ...o input interrupt data from the interrupt control Control output from control gates disabling I O decode when TIl is in ASPI cycle 3 6864 MHz output from clock generator which provides general timing for CPU and system communication logics components 1 8432 MHz input to 825lA from keyboard clock developed from CLK 2 H signal True low output from I O decode enabling TIl access of command register f...

Page 91: ...rious circuits and components for operation Control signal output from TIl used to enable various circuits and components for operation Control signal output from the control gates whenever a read activity involving a fast I O device is to occur Enable to mem map 8085 decoder to allow this device to decode inputs into video logic select signal Operational potential output to keyboard module J6 pin...

Page 92: ...mmunication logic and indicating DUART is ready to process data for a host device Select signal output from I O decode enabling TIl access of DUART in system communication logic for read write transaction Initialize system during power up sequence to known starting state Active outputs from I O enable gates whenever any address within the 17XXXX octal range is being output from the address latch S...

Page 93: ... RxD L Also used as status input to command register to report loopback condition Enables memory map to select mapped address values for output when true high and regular address values when false low Also used as status input to command register to report memory map on or off condition Most significant 8 bits of mapped 20 bit address output from the memory map Enables memory map 8085 decoder to d...

Page 94: ...and status registers within the system communication logic True low status input to command register from video logic whenever a monitor is hooked up to the system Selects signal output from I O decode enabling TlI access of NVR for read write transaction Selects signal output from I O decode which enables transfer of data from NVR RAM to NVR EPROM Status signal from ROM reserved for use with 32K ...

Page 95: ...ite control outputs from TIl defining type of read write transaction to occur Outputs from RAM address buffer which provide least significant four bits of column and row addresses to RAM for read write transactions or of row address for refresh transaction Outputs from RAM address output mux defining the most significant two bits of row address for refresh or read write transactions Reserved for u...

Page 96: ...refresh activity and false low output when address value is to be selected for RAM read write transaction Control signal output from control gates true high for read transactions Select signal output from I O decode enabling TIl access of data buffer in video logic for read transaction Used for transfer of data between the TIl via I O buffer and the various system I O devices Control signal output...

Page 97: ...originating at the keyboard module Til output providing two bit code to control gates with code value defining the type of transaction to occur Status signal input to command register low when Til has written data to character processor CP in video logic and high when last data written has been read by the CPo Programmable interrupt condition orginating at DUART in system communication logic 307 2...

Page 98: ... is to occur Select signal output from I O decode enabling Tll access of data buffer in video logic for write transaction Clock input to Tll from clock generator 7 3728 MHz Operating output to keyboard module via J6 pin 2 or via J8 Interrupt condition input to interrupt control from 8085 at video logic whenever the 8085 requires Tll access Select signal output from I O decode to reset 8085 device ...

Page 99: ...x RAM OAS ga tes RAM devices ROM devices TIl WR BUF GATE 8251A UART Logic Board Reference Numbers E41 E43 E45 Y2 E90 E48 E62 E91 E69 E47 E72 E90 E75 E74 E55 E68 E47 E54 J6 E27 E45 E62 E66 E67 E31 E69 E44 E31 E61 E62 E67 E133 E134 E71 E73B E152 E132 E151 E89 E135 E35 E53 E40 E69 E56 E50 E70 E83 E44 E47 E71 E72 E50 E42 E87 E86 E28 E35 E48 E49 EI E16 E19 E22 E39 E85 E23 E28 E44 E62 E44 E61 4 45 Schem...

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Page 101: ...ion or the host via the EIA host port or 20 mA port SYSTEM BOX Figure 5 1 VIDEO LOGIC LOGIC __ L _ _ __ _ SYSTEM COMMUNICATION LOGIC EIA PRINTER 20 rnA HOST PORT PORT PORT OPTIONAL HOST COMMUNICATIONS MONITOR IVR201 OR VR241 MA 0054 84 VT240 Series Terminal System Block Diagram 5 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 102: ...nd from the system communication logic 5 2 MAJOR CIRCUITS COMPONENTS Figure 5 2 is a block diagram that identifies the following major circuits components that make up the system communication logic 5 2 1 Dual asycronous receiver transmitter DUART Communications modern control COMM MOD CONTROL Communication multiplexer COMM MUX Printer interface PRINTER I F EIA host interface EIA HOST I F 20 rnA i...

Page 103: ... f o l J S J U CONTROLS MUX EIA HOST IIF L _ J L ___ J MA 0155 84 Figure 5 2 System Communications Logic Block Diagram 5 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 104: ... 2681 DUART s internal circuits and the CPU logic data lines TO FROM CPU LOGIC DATA LINES TO FROM CPU LOGIC DAO H RDA7 COMM RD L COMM WR L LDA2 H LDA5 HOST PRTR L HOST INTR1 L 2681 HOST INTR2 L DUART TIMER INTR L PRTR INTR1 L PRTR INTR2 L INIT H CLK2 H HOST TxD L TO FROM HOST RxD L COMM MUX MOD SPD SEL L TO EIA HOST HOST RTS L I F J5 HOST CTS L TO FROM EIA HOST MOD1 SI L I F HOST DTR L TO FROM HOS...

Page 105: ...ta Channel B Printer data to serial data port receive data RxD DATA BUS BUFFE RS DRD L W L B L_ OPERATION HOST PTR L CONTROL LDA2 H LDA5 H INIT H CLK 2 H TIMER INTR L HOST INTR2 L PRTR INTR 1 L PRTR INTR2 L converts printer port transmit output TxD B and serial printer B to parallel data OUTPUT PORT INPUT PORT HOST DTR L HOST RTS L MOD SPD SEL L PRTR DTR L HOST TxD L HOST RxD L TxD B RxD B PRTR DS...

Page 106: ... to program control read status and data transfer to and from the DUART CPU logic does this by addressing specific devices LDA2 H LDA5 H for read COMM RD L or write COMM WR L operations while the DUART is enabled HOST PRTR L Table 5 1 address Appendix values identifies the registers that can be addressed by read write operation and the involved circuit activity o provides a complete description of...

Page 107: ...channel Printer channel Printer channel Printer channel Printer channel Input port Output port Timing Output port Timing Output port 5 7 Register Mode register 1 and 2 Mode register 1 and 2 Status Data clock select Command Receive data Transmit data Input change Auxiliary control Interrupt status Interrupt mask Counter timer upper Counter timer upper Counter timer lower Counter timer lower Mode re...

Page 108: ... OR INTEGRAL MODEM COMMUNICI TION 5 HOST DTR L IS NOT USED BY THE 20mA I F 6 PRTR DSR L WILL BE SAMPLED BEFORE TxD B OUTPUT IF PRTR DSR L WAS NOT TRUE AT 2681 DUART POWER UP MA 0145 84 2681 DUART Transmit Data Timing Diagram Communication Modem Comm Modem Control The comm modem control circuitry provides Storage for communication and modem control data received from the CPU logic Information and s...

Page 109: ... Modem Control Circuits following breakdown of comm modem control Figure 5 7 shows the Communication Control Register COMM CTRL REG contains a write register for storing control data written by the CPU logic The stored control data define the enabled interface CSL0 H CSLl H output to the communication mux This register also contains controls for the integral modem if installed and a read register ...

Page 110: ...lOT 0 MOD SW HK H l CTRL TEST IND H u RD CCT H I I REG MOD A B L I I MODE SEL H DIAL TONE DET H I I I I MOD CTKL ROAD RDA5 RDA6 WR REG TI I WR MOD CTR L L I _ _ L IJI _ _ RD COM M CTRL LDAl LDA2 I I COMM MOD RD MOD CTRL L r WLB L I I DECODE WR COMM CTRL ORO L I I r i WR MOD CTRL L MODEM L _L _ _ L ____ J L ____ O R T R Y I E Figure 5 7 MA 017Q 84 Communication Modem Comm Modem Control Block Diagra...

Page 111: ...e CPU logic accesses various status LDAI while comm modem control registers to program control or read The CPU logic does this by addressing a specific register H LDA2 H for read ORO L or write WLB L operations the COMM MOD DECODE is enabled MODEM L Table 5 2 identifies the registers that can be addressed by address and read write operation Appendix 0 provides complete descriptions of the register...

Page 112: ...akdown of the comm mux Comm Output Mux converts DUART data and ready signals to data and ready signals to the selected interface only the data signal is passed on to the 20 rnA interface Comm Input Mux converts data and ready signals from the selected interface into data and ready outputs to the DUART only a data signal is input from the 20 rnA interface with HOST DSR L developed from PULL UP Late...

Page 113: ...agram TO FROM DUART PRTR DTR L TxD B RxD B PRTR DSR L Figure 5 9 5 I LINE 2 BUFFERS r 3 r r NOTE J2 PIN 1 IS NOT CONNECTED ON LOGIC BOARD J2 PINS 4 7 AND 9 ARE NOT USED J2 CD 108 2 S1 2 BA 103 D1 BB 104 D2 CC1107 M1 AB 102 E2 AA 101 E1 MA 0161 84 Printer Interface I F Block Diagram J2 is a nine pin EIA RS232C RS423 connector used to connect the terminal to a local auxiliary device La t e r in t hi...

Page 114: ...t connected to the 20 rnA port Figure 5 11 shows the following breakdown of the 20 rnA interface Transmit Optoisolator provides isolation between the TTL level transmit data signal 20 rnA TxD L at the terminal and 20mA level signals T T on the 20 rnA port communication lines Receive Optoisolator provides isolation between the TTL level receive data signal 20 rnA RxD L at the terminal and 20 rnA le...

Page 115: ...M4 CB 106 M2 CA 105 SE CH 111 S4 AB 102 E2 MA 01S2 84 Figure 5 10 EIA Host Interface IfF Block Diagram TO FROM COMM MUX 20mA TxD L 20mA RxD L NOTE TRANSMIT OPTOISOLATOR 12A RECEIVE OPTOISOLATOR J4 PINS 1 AND 8 PROVIDE OPERATIONAL VOLTAGE POTENTIALS FOR LOOPBACK TEST PINS 4 AND 6 ARE NOT USED AT J4 OR AT LOOPBACK CONNECTOR LOOPBACK J4 CONNECTOR r T 5 51 r T 2 2 12 V 1 R 7 3 R 3 r GND 81 MA 0146 84 ...

Page 116: ...OD2 DSR L 3 28 MOD2 CTS L MOD2 RxD L 4 27 MOD2 DTR L MOD2 SI L 5 26 TEST IND H MOD2 TxD L 6 25 RDL TEST H MOD2 SPD SEL H 7 24 ANL TEST H GND 8 23 NOT USED DATA AVAIL L 9 22 OH M H OH D L 10 21 SW HK H MOD 9 10 H 1120 CCT H MOD PRESENT L 1219 12V MOD DATA TALK L 13 18 NOT USED MOD AlB L 14 17 DIAL TONE DETECT H NOT USED 1516 DOM EUR L DOM EUR L NOT CURRENTLY IMPLEMENTED Figure 5 12 5 16 MA Q143 84 ...

Page 117: ...onic AA 191 El AB 192 E2 ANL TEST H BA 103 Dl BB 104 02 CA 105 SE NOTE The reference listing is based on Rev C of the schematics CS54l5495 9 l System Communication Logic Signal Descriptions Signal Name Protective Ground Signal Ground Analog Loop Test High Oa ta Output Oa ta Input Request To Send 5 17 Description Not connected at terminal Provides common ground Places integral modem in data loop te...

Page 118: ... ready for communication activity Indicates integral modem senses audio path to telephone line is ready Indicates terminal is ready for communication activity Indicates external modem senses good comm line Indicates receive speed greater than 600 bps selected in set up Directs terminal to use transmit and receive speeds of 1200 bps regardless of set up speeds 3 6864 MHz clock Enables read activity...

Page 119: ...A host CSL0 H C SLl H both low or 20 rnA CLS0 H LOW CSLI H high Requests data path through integral modem Indicates integral modem senses telephone line ready for dialing Not currently used Enables read outputs RD COMM CTRL L or RD MOD CTRL L when COMM MOD DECODE is selected MODEM L active Indicates external modem is ready for communication activity buffered CC l07 Ml Indicates terminal is ready f...

Page 120: ...t or external modem is ready to receive transmit data buffered CB 106 M2 Indicates host or modem is ready for communication activity Indicates terminal is is ready to transmit or receive Indicates host receive data is present Indicates DUART is ready for host transmit data Enables DUART for read write EIA host port serial receive data buffered BB 104 D2 Requests data path through remote modem buff...

Page 121: ...RTR L both low Defines integral modem to use 9 bi t high or l bit characters low Defines integral modem emulation of BELL 212A high or BELL l 3 V 21 low Indicates good comm line has been detected by either the integral modem MOD 2 CD L low to MOD CD GATE or remote modem MOD 1 CD L low to MOD CD GATE Indicates external modem senses a good receive comm line buffered CF 1 9 M5 Indicates integral mode...

Page 122: ...em serial receive data Selects mode for integral modem operation as either originate low or answer high Low whenever integral modem is installed External modem signal defining receive transmit speeds of 1200 bps regardless of set up selection buffered CI 112 M4 Integral modem signal defining receive transmit speeds of 1200 bps regardless of set up selection Indicates to modem integral or external ...

Page 123: ...ing each character buffered CC 107 Ml Active ready output to printer port device from power on buffered CD 108 2 S1 2 Indicates printer receive data is present Indicates DUART is ready for printer transmit data Used by comm mux to develop HOST DST L during 20 rnA port activity 20 rnA port serial receive data Enables COMM CTRL REG to output control values Enables MOD CTRL RD REG to output status Da...

Page 124: ...erial transmit data Indicates integral modem is in test mode Programmable interrupt Printer serial data buffered BA 103 Dl 5 V operating voltage Enables write outputs WR COMM CTRL L or WR MOD CTRL L when COMM MOD DECODE is selected MODEM L active Enables COMM CTRL REG to input controls Enables MOD CTRL WR REG to input controls Operating voltage output Operating voltage output Operating voltage out...

Page 125: ...alk inverter MOD DOM EUR inverter Printer I P buffers Receive optoisolator Transmit optoisolator Logic Board Reference Numbers Schematic Page Coordi na te E60 7 E59 7 E33 7 E34 7 e57 5 E54 17 E24 8 E29 30 E37 8 E50 Sl E66 8 8 7 17 E48 E66 9 ES8 7 E46 7 E73A S E46 7 E6l 17 E47 17 E32 E36 8 E17 ES2 R74 80 7 D6 C38 QS 6 E17 l8 E6l 8 C36 37 D3 S Q3 4 S 2S C7 D7 DS D3 b7 C4 D4 A7 D7 C2 D22 A6 D6 Bl Cl ...

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Page 127: ...he CPU logic The CPU logic communicates with the video logic to initialize operation define patterns define modes define output color values and identify new display data SYSTEM BOX Figure 6 1 VIDEO LOGIC LOGIC _ _ 4 _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 mA HOST PORT PORT PORT LOGIC BOARD INTEGRAL OPTIONAL HOST COMMUNICATIONS MONITOR VR201 OR VR241 I VT240 Series Terminal System Block Diag...

Page 128: ...cs processor and related circuits to read status program operating parameters or provide graphics image data for display The CP processes text characters for display after the CPU defines which characters to be processed This frees the CPU for other system tasks The CP Figure 6 3 consists of the following circuits components 8085A l Microprocessor Device controls and performs all CP functionality ...

Page 129: ... J I TIMING AND CONTROLS CLOCKS AND CONTROLS G 70 J f o I I I I I I I I IVIDEO IOUTPUTS I I I ENABLES o w o L_______________ _____________ _____ J MA 0362 B4 Figure 6 2 Video Logic Block Diagram Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 130: ...ocked into the buffer by the transition of the 85WR BUF L trail edge and read out by RD BUF L going low true Address Latch Generates the address used by 8085A 2 85LA0 H through 85LA7 H to access either graphics processor I O devices or CP memory with the address value clocked into latch by ALE Read Write R W Control generates the read write controls used by 8085A 2 to access I O devices Clock Buff...

Page 131: ...085A 2 internal circuits Serial I O Control is used for handshaking between the 8085A 2 and the TIl Interrupt Control RST 5 5 RST 6 5 interrupt condition access the relevant in CP memory monitors interrupt signal inputs and RST 7 5 determine when an exists and to force 8085A 2 to interrupt handling instruction code Register Array includes six general purpose register devices for 8085A 2 functions ...

Page 132: ...U logic Read write of CP memory Read write of graphics processor I O device circuits The CPU reads data from the 8085A 2 to determine operating conditions The CPU writes data to the 8085A 2 to define the specific CP memory address of a character to be processed over to the graphics processor circuits The 8085A 2 reads data from the CP memory to either access instruction codes acquire character for...

Page 133: ...rocessor I O circuits Note that although memory access can occur at any time the 8085A 2 is limited to I O access only during vertical sync time defined by GVS Hand GBLK H interrupt inputs Later in this chapter Table 6 6 describes the signals identified in these timing diagrams CLOCK 101M 101M ALE RDL RDLlWRL INSTRUCTION FETCH CYCLE NOTES READIWRITE CYCLE 1 101M SIGNAL FOR MEMORY READIWRITE TRANSA...

Page 134: ... that contains firmware that directs 8085A 2 operations as well as character pattern data NOTE CP ROM can consist of a single 32K device or two ROM devices with up to 32K storage If a 32K ROM is used it is installed in the ROM 7 position and ROM 8 is not used FROM ADDRESS S 85LAOH 85LA7H LATCH V c P 85A0AD7 FROM ROM 8085A2 85AD8H 85AD13H y FROM 8085A2 A15r ROM7 OE L C P_ MEMORY ROM8 OE L DECODE RO...

Page 135: ...BUF L Only one processor can use the video access circuit at given time Control over enabling access is the VID ACCESS L signal from the CPU logic When VID ACCESS L is low true the CPU has access when VID ACCESS L is high false the CP has access The video access circuit Figure 6 7 consists of the following components Video Address Mux consists of two mux devices that select CPU address values LDAl...

Page 136: ...BUF L 85WRBUF L VIO ri V RD GDC L tt RD VDM L VIO RD INIT CBADDR L iWRGDCL I WR VOM L IWR CHAR BUFF L WR RATWWLT L IWR MASK L I V WR VPAT L IWR LU L I WR REGO L WR REG1 L I WR HB SCROLL D A L I WR LB SCROLL D A L I VIDEO I J CPU VIDEO VDBO H VDB7H I TOIFROM DATA VIDEO 1 0 BUFFER f A V DEVICES 9 A CP 0 VIDEO DATA BUFFER Figure 6 7 Video Access Block Diagram 6 10 TO CP TO VIDEO 1 0 DEVICES MA 0367 8...

Page 137: ...bes the signals shown in Figure 6 7 Table 6 2 Video Access Circuit I O Addresses CPU Address CP Address Signal Octal Hex Destination Device RD GDC L 173000 173002 00 01 GDC WR GDC L 174000 174002 00 01 GDC RD VOM L 173040 173076 10 1F Video output map WR VOM L 174040 174076 10 1F Video output map 85 RD BUF L Not accessed 20 85 RD data buffer CP gate handshake F F 85 WR BUF L Not accessed 20 85 WR ...

Page 138: ...icroprocessor device FIFO Buffer is a 16 byte device that stores command information communication between the system IIF and FIFO is on a separate bus from the PD7220 internal bus Command Processor accesses and decodes commands stored in the fifo distributing parameter information to the various internal circuits Internal Bus Interface buffers communication between the system IIF and other intern...

Page 139: ...D MUX DEVICES MA 0368 84 Figure 6 8 Graphics Processor Block Diagram RDGDC L WRGDC L VAO H CK 2MZ L GND 5V SYSTEM I F FIFO BUFFER COMMAND PROCESSOR PARAMETER RAM Figure 6 9 GBLK H VIDEO GHS H SYNC GENE RATO R f Gc V S H ___ MEMORY GRAS L TIMING GDBEN L GENERATOR DRAWING PROCESSOR A16 MA 0369 84 PD7220 GDC Block Diagram 6 13 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE ...

Page 140: ...173002 for a write of parameter data to GDC FIFO WR GDC L low and VA0 H high or a read of status data from GDC status register RD GDC L low and VA0 H high All write operations are to the GDC FIFO with the VA0 H signal defining the data as either commands VA0 H low for address 173000 or parameters VA0 H high for address 173002 Commands define a specific operation type of parameter information to fo...

Page 141: ...ines per video field Generate and output vertical sync Cursor and character characteristics command followed by three parameter bytes parameter bytes define cursor on or off lines per character row cursor blink rate blinking or steady cursor cursor top and bottom line numbers in the row Start display scanning Blank display Cursor position command followed by three parameter bytes parameter bytes d...

Page 142: ... direction write data into display memory with data transfer defined as a word and RMW cycle logical operation defined as reset to zero Mask register load command followed by two parameter bytes defining a mask to control which bits can be modified in the bit map memory during RMW cycles Figure drawing parameters specify command followed by up to 11 parameter bytes parameter bytes define type of d...

Page 143: ...t address values CPU CP read of data from display memory command defining data read cycle to be a word with first low then high bytes read CPU CP read of cursor position with position of word and dot addresses supplied to CPU CP in five bytes CPU CP DMA read request command defining transfer as a word with low then high byte CPU CP DMA write request command defining transfer as a word with low the...

Page 144: ...ynchronization Figures 6 l through 6 15 are timing diagrams for various GDC operations Later in this chapter Table 6 6 describes the signals shown in these diagrams VAOH WRGDCL VDBOH VDB7H t j I TWCY SYMBOL PARAMETER MIN MAX UNITS TAW ADDRESS SETUP TO WR a NS TWA ADDRESS HOLD FROM WR a NS TWW WR PULSE WIDTH 100 NS TOW OATA SETUP TO WR BO NS TWO DATA HOLD FROM WR NS TWCY WR PULSE CYCLE 4 TCLK NS Fi...

Page 145: ...GDC Timing Diagram CPU CP Read Transaction 2 X CK 2MZ L GADO H GAD 14 H GAD15 H A16 GRAS L TDD GHSH GBLK H _______J_ ________A GVS H SYMBOL PARAMETER MIN MAX UNITS TAD ADORESS DATA DELAY FROM 2 X CCLK t 130 NS TOFF ADDRESS DATA FLOATING FROM 2 X CCLK t 10 130 NS TRR RAStDELAY FROM 2 X CCLK t 30 110 NS TRF RAStDELAYFROM2XCCLK t 90 NS TDD VIDEO SIGNAL DELAY FROM 2 X CCLK 120 NS MA 0372 84 Figure 6 1...

Page 146: ... AI HORIZONTAL r 1 H ______ v v v v ___ GAO GAO _ _ __ _ _ _ _ _ _ _ _ _ __ x I J V __ J __ _ x __________ _ x I xl __ l x X x x X __ _ LCOA ROWI ROWI I G BLK L I L GVS L lV l BI VERTICAL MA 0373 84 Figure 6 13 PD7220 GDC Timing Diagram Video Sync Signals Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 147: ...RESS OUT D GDBENL _ _ _ _ _ RMWH ENDH l ___________________________________ RASL r l RAHH LAS L A15 EPSH A14 EBSH DAD3 DAD3 DATA OUT 0 0 0 0 Figure 6 14 PD7220 GDC Timing Diagram 2 P1ane Write Transaction 6 21 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 148: ...deo DMA write Transaction 6 2 5 Timing and Control Circuits MA 0375 84 The timing and control circuits following circuits Figure 6 16 consist of the Clock generator ROM address counter Timing signal generator BLANK generator BEN and STOP gates Read modify write RMW generator 6 22 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 149: ...or Block Diagram 6 2 5 1 Clock Generator The clock generator provides the basic timing signals used by various video logic components The clock generator Figure 6 17 consists of the following components Yl is an oscillator that provides basic clock 16 097280 MHz L10 C47 is a filter for 16 MHz clock outputs Divider generates 8 MHz CK 8 MZ L and 2 MHz CK 2 MZ L clocks from buffered input from Yl 6 2...

Page 150: ... from STOP gate is true low ROM Address Clock Counter generates address value output A0 H A3 H from CK 16MZ H input Later in this chapter Table 6 6 describes the signals shown in Figure 6 19 6 2 5 4 Timing Signal Generator The timing signal generator provides control for video logic activity by generating control outputs based on cyclically addressed ROM based firmware The timing signal generator ...

Page 151: ... AND STOP L STOP GATES Figure 6 20 TO BIT MAP MA 0378 84 BEN and STOP Gates Block Diagram ROM TO ADDRESS TIMING SIGNAL CLOCK GEN TO P S CONVERSION MA 0379 84 ROM Address Counter Block Diagram FROM ROM 5V SCROLL STOP F F ADDRESS L _ _ _ COUNTER A4 TIMING TMO SIGNAL BUFFER END H RAS H CAS H GAS H TO DBIN L VARIOUS LLB L CIRCUITS SYNCH H SEL LB MA 0380 84 Timing Signal Generator Block Diagram 6 25 Ar...

Page 152: ...mset input from ERASE F F ERASE F F is clocked by the trailing edge of RAS H input with a low output when ERASE L input is true forcing RMW F F to output true RMW control signals Later in this chapter Table 6 6 describes the signals shown in Figure 6 21 FROM TIMING SIGNAL GENERATOR FROM MODE SELECT FROM TIMING SIGNAL GENERATOR RAS H ERASE L 5V FROM BEN GATES GDBENH BGD BEN L Figure 6 21 END H ERAS...

Page 153: ...NK I L output from BLANK L input and D BLANK buffer which generates D BLANK L output to D A Both are clocked by CK l6MZ H with three clocks needed to reflect any change in BLANK L input at D BLANK L output Later in this chapter Table 6 6 describes the signals shown in Figure 6 22 FROM Gac FROM G BLK H TIMING RAH H SIGNAL SYNCH H GENERATOR FROM CLOCK CK 16MZ L Figure 6 22 SBLANK F F BLANK F F FROM ...

Page 154: ...map addressing circuit refer to section 6 2 7 2 Vector pattern register in pattern select circuit refer to section 6 2 10 Depending upon how these various components are programmed the video logic can operate in one of the following six different write modes Mode 0 Read Back Mode defines a read back of bit map for hardcopy and diagnostic purposes FROM VIDEO ACCESS WR REGl L WR REGO L VDBl H VDB3 H...

Page 155: ...for the mode select registers Appendix E provides descriptions of the bit values of for the various components used for each of the six write modes 6 2 7 Bit Map Addressing Circuit The bit map addressing circuit generates row and column addresses for accessing the bit map The bit map addressing circuit Figure 6 24 consists of the following circuits Plane and byte select Address select Row column m...

Page 156: ...h DAD3 L low when either ANDed pair are both highs FROM TIMING AND CONTROL FROM TIMING AND CONTROL RMW L FROM MODE SEL GDC H SEL DAD L SELECT DAD LAD eS BL A Nc K eL_ _ _ _ t DECODE R SEL LAD L FROM MODE SELECT SCROLL EN L TO EPS L BIT MAP EPS H EPS H WRITE ENABLE r _ __ l l EP eS Hc TO P S rgGIC CONVERTER UNIT PLANE FROM RAS H TIMING AND CAS H CONTROL EPS j E PS L _ _ EBS EBS H GEN J I PLANE AND ...

Page 157: ...column mux Generate LAD1S H LAD16 H output values based on GDC input whenever GDC address values are selected for output to the row column mux LAD1S H LAD16 H values are used at the plane and byte select circuit to determine plane and byte select values to be supplied to the row column mux The address select circuit Figure 6 26 consists of the following components Scroll Address Counter consists o...

Page 158: ...umn address values Later in this chapter Table 6 6 describes the signals shown in Figure 6 27 6 2 8 High Low Hi La Byte Select The hi l a byte data GAD0 H GADlS H for circuits GD0 L select circuit selects either GDC low order byte GAD7 H or GDC high order byte data CAD8 H output to the mask select and write data select GD7 L during RMW cycles The hi lo byte select circuit following components Figu...

Page 159: ...AD7H M _ GAD8H GAD15H AND R M W L ______________ CONTROL FROM EPS L BIT MAP HI LO BYTE MUX I I I MUX TO WRITE DATA SELECT TO BIT MAP WRITE ENABLE SELECT I LB H TO r BITMAP ADDRESSING MA 0388 84 Figure 6 28 Hi La Byte Select Block Diagram LB H Generator monitors GADS H GADl5 H bus lines to generate high true LB H output when anyone of the high byte GAD signals is an active high true Later in this F...

Page 160: ... hi lo byte select inputs originating at the GDC GD0 L GD7 L when VEC H is high write Mask Latch generates the write enable outputs during RMW L low with the write enables based on the last enabled mask select mux input to the latch FROM VIDEO VDBOH VDB7H ACCESS FROM HI LO GDOL GD7L BYTE SELECT FROM TIMING RMW L AND CONTROL FROM EPS H MASK SELECT 1 _ MUX BIT MAP FROM VEC H ADDRESSING MODE SELECT V...

Page 161: ...onsists of the following circuits components Character Pattern Address Counter counts up from a zero starting value loaded by RD INIT CB ADDR L low with incrementing output used as the address value for character pattern buffer Counter Clock Gate enables counting by character pattern address counter only when the character pattern bufffer is not being loaded Character Pattern Buffer consists of tw...

Page 162: ... PLI ER REGISTER WR PAT MULT L CHARACTER PATTERN BUFFER FROM MODE SELECT SELVPATH PATTERN MULTIPLIER COUNTER IMULTIPLEXER I CLOCK LOAD T _ PATTERN REGISTER IREGISTER I e T Figure 6 30 Pattern Select Block Diagram 6 36 8 BIT PATTERN TO LOGIC UNIT MA 0390 84 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 163: ...n in Figure 6 30 6 2 11 Logic Unit The logic unit converts data input from the bit map into new write pattern data output to the write data select circuit This conversion is based on the pattern either character or vector input from the pattern select circuit bit map data input from the bit map and control values loaded into the logic unit circuit by the CPU or CPo The logic unit circuit Figure 6 ...

Page 164: ... are opposite values and high to the logic unit when both signals have same value Low to high transition indicates that intensity values for the selected plane are being passed by the intensity select mux Logic unit consists of two four bit algorithm logic unit ALU devices that manipulate inputs from the bit map MD0 H MD7 H pattern select and other logic unit components into a write pattern WP0 L ...

Page 165: ...ulated internal to the GDC or to the bit map during DMA write mode The write data select circuit following components Figure 6 32 consists of the DMA Buffer generates data output to the bit map when DMA is enabled SEL SD H high Write Data Select Mux generates data output to the bit map when DMA is disabled SEL SD H low from either the hi lo byte select SEL EXT LU H low or logic unit SEL EXT LU H h...

Page 166: ... Buffer Gates is enabled by VEe L high to pass bit map data outputs to the read back buffer FROM C A S H________ TIMING LLB L AND CONTROL DBEN L FROM MODE VEC L SELECT GADO H GAD15 H TO WRITE DATA SELECT TO LOGIC UNIT TO TO GDC P S CONVERTER FROM BIT MAP _ _ _ JI WRITE ENABLE WRITE ENABLES I FROM BIT MAP MADO H MAD7 H ADDRESSING I FROM CASH TIMING AND MDO MD1 MD2 MD3 CONTROL RAS H I FROM WRITE DAT...

Page 167: ...34 consists of the following circuits components Bit Select BS Gate gates EBS 1 and DAD3 1 input with Scroll enable inputs to generate a BS H value to the gate decoder BS H low for selecting the low order bit BS H high for the high order bit Gate Decoder is enabled by RMW L low to decode plane EPS H and bit BS H inputs into single gate enable output for the selected plane and bit G0 one for plane ...

Page 168: ...consists of four eight bit shift storage registers one high byte and one low byte PIS converter for each plane Each register is clocked by CK 64MZ H gated by gate decoder input and controlled by PIS mode select buffer input Serial output from each is sent to the PIS output buffer PIS Output Buffer selects either plane zero and one high bit values P0 HB H and Pl HB H when SEL LB L is high or plane ...

Page 169: ...or output map values one RAM device for the upper four bits of map0 through map3 and one for the lower four bits Memory is written to by CPU or CP when WR VOM L is low and VOM output when WR VOM L is high VOM Address Select enables CPU or CP access when EN VOM H is low address mux device passes VA0 H VA3 H inputs and video logic access when EN VOM H is high address mux passes VOM0 H VOMI H while t...

Page 170: ... BUFFER VOM VDBOH VDB7H WR VOM L SHARES SAME PHYSICAL COMPONENT 2918 VOM BUFFER WITH DBLANK GENERATOR OF TIMING AND CONTROL VBDOH VDB7H VOM READ BACK REGISTER VBOH VB1H VMOH VM1H Figure 6 35 Output Map Block Diagram 6 44 TO VIDEO ACCESS TO D A MA 0395 84 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 171: ...MAP1 BYTE2 1771354 16H 1 13 13 1 MAP1 BYTE3 1771356 17H 1 13 1 1 MAP2 BYTE13 17713613 18H 13 1 13 13 MAP2 BYTE1 1771362 19H 13 1 1 13 MAP2 BYTE2 1771364 1AH 13 1 13 1 MAP2 BYTE3 1771366 1BH 13 1 1 1 MAP3 BYTE13 17713713 1CH 1 1 13 13 MAP3 BYTE1 1771372 1DH 1 1 1 13 MAP3 BYTE2 1771374 1EH 1 1 13 1 MAP3 BYTE3 1771376 1FH 1 1 1 1 Table 6 5 Intensit Definition for Output Map Outputs Vx13 H Vx1 H Inten...

Page 172: ...lor or monochrome monitors NOTE J8 can also be used for output of keyboard data output FROM TxDH 15 KY8D R D H IIF x 14 TO MONITOR PRES L 13 CPU 12VC 8 GVS H FROM GDC GHS H 1 6 11 10 9 12 VRO H VR1 H I I VR INPUT IVR OUTPUT STAGE STAGE VGO H VGINPUT VG OUTPUT STAGE STAGE VG1 H VBO H VB INPUT VB OUTPUT STAGE STAGE VB1 H VMOH VM INPUT VM OUTPUT STAGE STAGE J8 TO MONITOR J7 MA 0396 84 Figure 6 36 Dig...

Page 173: ...lar PNP transistor networks that generate the actual video outputs to the monitor VR output stage shown in Figure 6 36 VB output stage identical to VR VG output stage has the 348 ohm resistor replaced by a 332 ohm resistor for input of sync value VM output stage has the 348 ohm resistor replaced by a 200 ohm resistor for input of sync value and the capacitor is replaced by an NPN transistor networ...

Page 174: ...ow Enables address latch to input 85AD0 H 85AD15 H signals from CPo Buffered version of GO BEN L from GDC True control signals during screen blank periods developed from G BLK H high as synchronized by SYNC H and CK 16 MZ L True low signal during screen blank periods developed from BLANK Land used to develop 0 BLANK L Used by gate decoder in piS converter circuit to define whether high BS H high o...

Page 175: ...GDC access to GDC data bus lines gated from BGD BEN L buffered version of GO BEN L from GDC and 0 BIN L are both true Control signal output of timing signal generator coordinating GDC access to GDC data bus lines by providing enable 0 BIN L low or disable 0 BIN L high to 0 BEN L gate Active low during screen blank periods used at D A to force all video signal outputs to blank level Control output ...

Page 176: ...igh to RMW genera tor Coordinates plane select activity with EPS Hand EPS L signals going true on first CAS H true after RAS H true condition Register 0 output defining erase condition when low Gate inputs to each of the four PIS converter devices one gate for each and one gate at a time active defining which bit of which plane is processed GDC Address Data Lines zero GDC bus lines used for transf...

Page 177: ...utput defining vertical sync period Low input from GDC to video access circuit to access a video logic component for a write transaction Defines background intensity factor to logic unit for either plane zero developed from IB 3 H or plane 1 developed from IBI H Background intensity values from logic unit register Defines foreground intensity factor to logic unit for either plane zero developed fr...

Page 178: ... originating at GDC SCROLL EN H low input to latched address mux or scroll address counter SCROLL EN H high Timing signals generator output enabling bit map output data to be loaded into bit map read back buffer when low M0 H Ml H Mode Select Bit 0 and 1 Control outputs from logic MAD0 H MAD7 H MD0 H MD7 H MDI0 H MDI7 H High unit register defining mode of operation to logic unit Memory Address Bit...

Page 179: ...gle bit of plane 3 low order byte PIS converter devices output for single bit of plane 1 high order byte PIS converter devices output for single bit of plane 1 low order byte Vector pattern based on pattern register data as multiplied by factor in pattern multiplier register Logic unit register value used during single plane write operations to define plane to be affected as plane 3 PS L low or pl...

Page 180: ...IO M low for read Low input from CPU to read data from 81385 RD buffer also resets handshaking F F Low output from video access circuit when CPU CP is to access GDC for read Low output from video access circuit when CPU CP wants to initialize character buffer address counter Low output from video access logic when CPU CP is to access YOM for read Data bus lines for transfer of data between video l...

Page 181: ... and developed from G BLK H high inverted input synchronized to RAH H Mode select input to piS converter device used to convert plane zero low order byte to serial data P0 LB H Mode select input to PIS converter device used to convert plane one low order byte to serial data PI LB H Mode select input to PIS converter device used to convert plane zero high order byte to serial data P0 HB H Mode sele...

Page 182: ...fied data written to bit map when SCROLL EN H is high and SEL SD H is low Low outputs from DAD LAD decoder only when SCROLL EN H is low for GDC access of bit map screen is blanked S BLANK L low with SEL LAD L low when read back mode is selected SEL GDC H is high and SEL DAD L low tied to RMW cycles RMW L low during other than read back mode SEL GDC H low with DAD LAD outputs used at plane and byte...

Page 183: ...H low Timing signals generator output to piS converter selecting P0 HB H PI HB H output to output map SEL LB L high or P0 LB H PI LB H SEL LB L low Control output from register one used to enable write data select circuit to output data to bit map from bit map SEL SO H high GDC SEL SO H low and SEL EXT LU H low or logic unit SEL SO H low and SEL EXT LU H high Control output from register zero used...

Page 184: ... the timing signals generator used to synchronize blank signal generation Serial keyboard data output routed through the monitor connector J8 Address bits originating at CPU CP and used to address VOM when VOM access by CPU CP is enabled by EN VOM H low VA0 H is also used for address input to GDC Address bits originating at CPU CP and used by video access to decode video logic I O device to be ena...

Page 185: ...o access I O device for read Low to video I O decode whenever CPU CP is to access I O device for write Output map two bit code to D A for mono Output from register zero defining which output map is to be addressed map 3 map3 during video logic access of VOM Output map two bit code to D A for red Data output from logic unit used as data for bit map when write data select circuit is enabled to pass ...

Page 186: ...address counter Low output from video access for CPU CP write of low byte data to scroll address counter Low output from video access for CPU CP write to logic unit register Low output from video access for CPU CP write to write mask register Low output from video access for CPU CP write to pattern multiplier register Low output from video access for CPU CP write to register zero Low output from v...

Page 187: ...P memory decode to define enable 0 ROM7 ROM7 OE L low or ROM8 ROM8 OE L low and as most significant bit of ROM address Low input to video access from CP R W control when CP is to access I O device for read Low input to video access from CP R W control when CP is to access I O dvice for write Low order address for memory or I O access by CPo Low output from video access when CP is to read data from...

Page 188: ...x select gate Pattern multiplier counter Schematic Reference Numbers Page Coordinate El133 E136 E137 E1S9 E141 E1713 E177 E137 E1S7 E1S9 El16 9 CS 18 A4 A6 B3 14 D1 D3 18 A1 A4 18 Al E1413 18 CS E1313 E14S E178 13 BS CS IS C7 E18S E192 IS E1S8 E1S9 18 E77 El139 lS El131 9 El139 113 E1S13 9 El132 9 Ell313 9 E131 9 El138 113 El137 113 E187 18 E188 18 EllS 16 E77 E78 E93 13 E136 E138 18 E167 E169 18 ...

Page 189: ...Yl 8085 read buffer 8085 write buffer Schematic Reference Numbers E64 E78 E79 E186 E190 E139 E94 E109 E146 E147 E165 E166 E189 E129 E126 E144 E96 E191 E122 E141 E69 El19 E168 E120 E128 El17 E136 E157 El10 El13 E137 E158 E159 E77 E83 E148 E149 E82 R100 R101 E84 R98 R99 R102 R103 C45 E82 R96 R97 E84 R92 R95 C44 E88 E104 E76 E92 El17 El18 E83 R106 R107 E84 R104 R105 R108 R109 Rl12 Rl14 C46 C48 Ql Pag...

Page 190: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 191: ...he CPU logic is full duplex serial and asynchronous at 4800 bits per second bps The communication lines conform to EIA standard RS 423 which applies to imbalanced voltage interfaces SYSTEM BOX Figure 7 1 VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 mA OPTIONAL HOST PORT PORT HOST PORT COMMUNICATIONS MONITOR IVR201 OR VR241 MA OOS4 84 VT240 Series Terminal System Block Diagr...

Page 192: ...ranged in the following four groups Figure 7 2 Main keypad 57 keys Numeric keypad 18 keys Special function keypad 20 keys Editing keypad 10 keys Figure 7 2 LK201 Keyboard 7 2 KEYPAD NUMERIC KEYPAD Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 193: ...nnects the keyboard to the video monitor The keyboard transmits four signals to the monitor which pass unchanged to the system box via the video cable Figure 7 3 The four signals are as follows 12 V power to keyboard Ground to keyboard Serial out transmit line from keyboard Serial in receive line to keyboard You can place the cable in a channel in the bottom case and the modular type telephone con...

Page 194: ...P I I P DECODER 8 0 1 1 0 I I R 18 1 I 1 T I 2 CONN I KB DRIVE 1 to detect changes in the keyboard KEYBOARD LEOs f 5V LED 4 CONTROL SUPPLY CIRCUIT BEEPER BEEPER 3 CONTROL 2 MS CIRCUIT rn IL BEEP KEYCLICK 0 17 I S EEP BELL CONN ON OFF KB 1 KEYBOARD P 1 i 2 KHZ MATRIX DATA 0 1 18 X 8 LINES 8 0 7 1 o 1 TIMING _J NETWORKS 8051 MICROPROCESSOR I I I I P JUMPERS FOR 10 HARDWARE 10 I R IT I 3 I I RECEIVE ...

Page 195: ...the 8051 controls each of the four indicators The firmware responding to commands received from the CPU turns the indicators on or off 7 3 2 Keyboard Firmware Functions This section describes the keyboard firmware functions The functions are divided into two categories functions that cannot be changed by CPU instructions and functions that can be changed by CPU instructions 7 3 2 1 Functions follo...

Page 196: ...ons from the CPU These commands are categorized as transmission commands and peripheral commands Transmission commands contain a mode set command and an autorepeat rate set command Peripheral commands contain a variety of commands Refer to section 7 5 5 3 for more information on peripheral commands 7 4 Detailed Keyboard Circuit Description This section describes the keyboard circuit Figure 7 4 sho...

Page 197: ...e 8051 microprocessor and are called KB DATA 0 7 The 8051 scans the 18 drive lines Key closures are detected by reading the eight data lines The complete matrix is scanned every 8 33 ms When a key closure is detected it is scanned again to verify that it is really a key closure and not electrical noise Once the key closure is verified the 8051 firmware translatea the position information into a ke...

Page 198: ...yboard matrix on the LK201 AA American keyboard Keycap designations are listed for reference only you can compare them to Figure 7 7 A and B B C 3 DRIVE LINES r 2 DATA LINES 1 CONDITIONS ARE SWITCHES B2 B3 AND C3 CLOSED SWITCH C2 OPEN LINE 2 IS BEING DRIVEN AND LINE C IS BEING READ 2 INTERSECTION C2 IS BEING LOOKED AT IT SHOULD NOT SHOW A KEY CLOSURE BECAUSE SWITCH C2 IS OPEN 3 HOWEVER A SNEAK PAT...

Page 199: ...0 G16 4 F20 G23 N9 022 N8 021 T C17 PREV SCREEN 017 3 PF4 E23 r B17 N5 C2l N7 020 011 2 1 N N Note 1 023 C23 N6 N3 C22 B22 N2 B1B B2l N4 Nl C20 B20 Reserved Cll 1 Note that N0 N9 N_ N refer to the numeric keypad o ENTER A23 N A22 N0 See Note 2 N0 A20 Reserved 2 N0 of the numeric keypad can be divided into two keys Normally only the N0 keyswitch is implemented as a double size key 3 The RETURN key ...

Page 200: ...r J9 9 Reserved Fll Reserved Reserved I K J 8 I GIl Er J8 Dr J8 Cr J8 Br J8 f 8 Reserved MAIN Reserved EXIT U J M SCREEN 7 Gr J8 Gr J9 Er J7 Dr J7 Cr J7 Br J7 7 Reserved CANCEL Reserved RESUME Y H N 6 Gr J7 Gr J6 Er J6 Dr J6 Cr J6 Br J6 6 Reserved Reserved Reserved INTER T G B RUPT S Gr JS Er JS Or JS Cr JS Br JS S SETUP FS Reserved R F V SPACE 4 Gr J2 G03 E04 004 C04 B04 A01 Ar J9 Artisan Technol...

Page 201: ... 3 3 E03 w D02 1 E01 2 E D03 S C02 Q C01 1 Note that N0 N9 N_ N refer to the numeric keypad 1 D C03 x B02 A B01 3 C B03 B00 z 2 N0 of the numeric keypad can be divided into two keys Normally only the N0 keyswitch is implemented as a double size key 3 The RETURN key also canb e divided into two keys The one that is decoded as return is the RETURN C13 key Artisan Technology Group Quality Instrumenta...

Page 202: ...F5 Interrupt Resume Cancel Screen EXit ESC BS IF Options _ _ _ _ ____ F F18 F19 F20 DDDOOnODODDnODODnBI Do II IULJUU f IDD u D JEJ rJ D J D D tu LJLJEJ D E DDDD IShih 1 D J DD IShih 1 i _ i i i i Figure 7 7A LK201 AA Keyboard Layout LJLJLJLJ D D t 1 ID Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 203: ...GG I 699 IGGGGGGGGGGGI 611 I GGG GGGn I A99 II A0l1oA09 I I A20 IGl J NOTE THE GRAPHIC CHARACTERS ARE SHOWN FOR ILLUSTRATION PURPOSES ONLY AND ARE NOT MEANT TO ASSIGN KEYCAP USAGE OR LEGENDS Figure 7 7B LK201 AA Keyboard Layout Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 204: ... binary combinations on the inverter inputs All highs give the softest sound and all lows give the loudest sound The firmware controls the keyclick independently The bell tone is sounded only system control processor The keyclick disabled under the following conditions When a key is pressed When a metronome code is sent and the bell tone upon request from the is sounded unless When a command to so...

Page 205: ...051 PORT 2 74LS05 INVERTERS 12V L l II 5V HIGH E1 r _ _ ______ 5V Figure 7 9 HIGH SIGNAL FROM 8051 PROVIDES PATH THROUGH LAST STAGE OF OPEN COLLECTOR INVERTER TO TURN ON LED MA 0268 B2 Indicator LED Control Circuit 7 15 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 206: ...tures that can be enabled by commands from the CPU There are two categories of features one sets keyboard transmission characteristics and the other controls keyboard peripherals A peripheral command covers indicator control bell and keyclick loudness keyboard ID code and reinstate keyboard The commands come from the CPU and pass through the video cable monitor and keyboard cable to the receiver a...

Page 207: ...All jumpers are installed so the keyboard hardware ID is zero 7 4 7 Voltage Supplies The only voltage sent to the keyboard is 12 V However 5 Vand 10 V are also required These voltages are derived from the 12 V There is a 5 V supply that handles most of the requirements for this voltage The four keyboard LEDs have their own 5 V supply A 10 V supply provides voltage for the driver in the serial out ...

Page 208: ...L C99 Horizontal cursors B16 and B18 vertical cursors B17 and C17 Six keys directly above the cursor keys 016 018 and E16 E18 Function keys G99 G03 Function keys G05 G09 Function keys GIl G14 Function keys G15 G16 Function keys G20 G23 7 18 Representation 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE ...

Page 209: ...Options Reserved Reserved Help 00 Reserved F17 F18 F19 F20 Reserved Reserved Find Insert here Remove Select Previous screen Next screen Reserved 7 19 Keycode Decimal 086 087 088 089 090 091 098 099 100 101 102 103 104 105 110 III 112 113 114 115 116 117 122 123 124 125 126 127 128 129 130 131 132 135 136 137 138 139 140 141 142 143 144 Keycode Hexidecimal 56 57 58 59 SA 5B 62 63 64 65 66 67 68 69 ...

Page 210: ...20 7 157 9D D21 8 158 9E D22 9 159 9F D23 160 A0 E20 PFI 161 Al E21 PF2 162 A2 E22 PF3 163 A3 E23 PF4 164 A4 Reserved 165 A5 Cursor Keys 7 Reserved 166 A6 B16 Left 167 A7 B18 Right 168 A8 8 B17 Down 169 A9 C17 Up 170 AA Reserved 171 172 AB AC Shift Lock CTRL A99 and A10 6 Reserved 173 AD B99 B11 Shift 174 AE C99 CTRL 175 AF 5 C00 Lock 176 B0 A99 Compose 177 Bl Reserved 178 B2 7 20 Artisan Technolo...

Page 211: ...phics Keys and Spacebar 1 E00 E01 D01 C01 B01 E02 D02 C02 B02 B00 E03 D03 C03 B03 E04 Tilde 1 Q A Z Reserved 2 W S X Reserved 3 E D C Reserved 4 7 21 Keycode Decimal 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Keycode Hexidecimal B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF D0 Cl C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 Arti...

Page 212: ... H 221 DO B136 N 222 DE 1 Reserved 223 OF E137 7 224 E13 0137 U 225 El C137 J 226 E2 B137 M 227 E3 Reserved 228 E4 C138 8 229 E5 0138 I 2313 E6 C138 K 231 E7 B138 232 E8 Reserved 233 E9 E139 9 234 EA 0139 13 235 EB C139 L 236 EC B139 237 ED Reserved 238 EE El13 13 239 EF 0113 P 2413 F13 Reserved 241 Fl Cl13 242 F2 Bl13 243 F3 Reserved 244 F4 E12 245 F5 012 246 F6 C12 I 247 F7 Reserved 248 F8 7 22 ...

Page 213: ...e when the key is first pressed If the key is held down past the specified timeout period usually 31313 to 51313 ms a fixed metronome code is sent at the specified rate until the key is released Down up The keyboard transmits a keycode when the key is pressed and an up code when the key is released If any other DOWN UP keys are pressed the up code is a repeat of the down code If no other DOWN UP k...

Page 214: ...generated for an autorepeating keycode or special code may be transmits this special code instead of and then returns to the autorepeated autorepeated is always the last byte The a key is held down This produces the following transmission a metronome metronome Now the SHIFT key is pressed This produces the following transmission a metronome metronome shift a metronome Now the SHIFT key is released...

Page 215: ...wn with one command This and other autorepeat commands are grouped with the peripheral commands refer to 6 5 5 3 7 5 2 2 Special Considerations Regarding Down Up Mode If two DOWN UP keys are released simultaneously within the same scan and there are no other DOWN UP keys down on the keyboard only one ALL UPS code is generated 7 5 2 3 Autorepeat Rates There are four buffers in the keyboard to store...

Page 216: ...d is sent from the system module to enable the keyclick on the C99 key the keyclick is generated refer to section 7 5 5 3 Figure 7 7 shows the positions of these keys The keyclick or bell or both may be disabled When the keyclick or bell is disabled it does not sound If the system module requests sound refer to section 7 5 5 3 the keyclick or the bell does not sound Both the keyclick and bell may ...

Page 217: ...MODE ACK PREFIX TO KEYS DOWN MODE CHANGE ACK RESERVED Keycode 179 decimal B3 hexidecimal Keycode 180 decimal B4 hexidecimal keycode 181 decimal B5 hexidecimal Keycode 182 decimal B6 hexidecimal Keycode 183 decimal B7 hexidecimal Keycode 184 decimal B8 hexidecimal Keycode 185 decimal B9 hexidecimal Keycode 186 decimla BA hexidecimal Keycode 127 decimal 7F hexidecimal ALL UPS indicates to the system...

Page 218: ...ocessed a indicates that the keyboard has mode change command refer to section RESERVED keycode 7F is reserved for internal use The following four special codes have values below the 6410 range KEYBOARD ID firmware KEYBOARD ID hardware KEY DOWN ON POWER UP ERROR CODE POWER UP SELF TEST ERROR CODE Keycode 01 decimal 01 hexidecimal Keycode 00 decimal 00 hexidecimal Keycode 61 decimal 3D hex idecima ...

Page 219: ...the corrected four byte power up sequence when the pressed key is released This avoids a fatal error condition if a key is pressed by mistake while powering up The keyboard LEOs are lit during the power up self test If the self test passes the keyboard turns the LEOs off If a bell is selected on powerup the system module can transmit a sound bell command to the keyboard However this should not be ...

Page 220: ...ds Mode set Autorepeat rate set Peripheral Commands Flow control Indicator Audio Keyboard ID Reinitiate keyboard Some autorepeat control Jump to test mode Reinstate defaults The high order bit of every command is the PARAMS flag If there are any parameters to follow the PARAMS flag is clear If there are no parameters to follow the PARAMS flag is set 7 5 5 2 Parameters The high order bit of every p...

Page 221: ... an error code Each keyboard LED can be turned on and off The following eight commands control the keyclick and bell sounds Disable keyclick Enable keyclick and set volume Disable CNTL keyclick Enable CNTL keyclick Sound keyclick Disable bell Enable bell and set volume Sound bell The following four commands are related to control over the autorepeat mode Temporary Autorepeat Inhibit stops autorepe...

Page 222: ...peat buffer selections Audio volume Control key keyclick To send a peripheral command set the TYPE flag low order bit Bits six three contain a command representation from the chart below Bits two and one specify on 01 off 00 or sound 11 Bit seven should be set if there are no parameters to follow Table 7 4 lists the peripheral commands in hexidecimal Command Flow control Indicator LEDs Keyclick Be...

Page 223: ... Autorepeat Temporary autorepeat inhibit Enable autorepeat across keyboard Disable autorepeat across keyboard Change all autorepeat to down only Other Request keyboard 10 Jump to power up Jump to test mode Reinstate defaults 7 33 Hex 8B 89 13 11 99 lB B9 BB 9F Al 23 A7 Cl E3 El 09 AB FD CB 03 Parameters None None Bit pattern Bit pattern None Volume None None None None Volume None None None None No...

Page 224: ...ators LEOs Figure 7 12 shows the LED parameter Figure 7 13 shows the LED layout on the LK201 keyboard Audio Figure 7 14 shows the audio volume parameter MA 0179 82 Figure 7 12 Indicator LED Parameter o 0 0 0 LED 4 LED 3 LED 2 LED 1 MA 0176 82 Figure 7 13 Indicator LED Layout 07 06 05 04 03 02 01 00 I1 I 0 0 I 0 I 0 I 3 BI VOL ME MA 0177 82 Figure 7 14 Audio Volume Parameter 7 34 Artisan Technology...

Page 225: ...Down Only changes division settings for all autorepeating divisions to down only Request Keyboard IO causes keyboard to send a two byte keyboard ID Keyboard does not jump to powerup Reinitiate Keyboard causes keyboard to jump to its powerup routine The system module should not try to transmit anything to the keyboard until the last byte of the power up sequence is received Jump To Test Mode produc...

Page 226: ...e are parameters Autorepeat Rate Buffer Association If autorepeat mode is selected the system module can transmit a parameter to change the buffer association of the selected division Refer to section 7 5 2 3 for autorepeat rates and section 7 5 7 for default values Figure 7 16 shows a set main array to autorepeat changing buffer association to buffer 3 Autorepeat Rate Buffer Values At keyboard po...

Page 227: ... 1 I 0 1 I 0 1 0 0 0 0 0 1 1 MA 0181 82 Figure 7 16 Set Main Array to Autorepeat Example RATE CHANGE PARAM COMMAND BUFFER NO TYPE A r ____A _ _ 07 06 05 04 03 02 01 00 0 1 I 1 I 1 I 1 I 1 I 1 I 0 0 PARAMETER 1 TIMEOUT 1 PARAMETER 2 INTERVAL MA 0182 82 Figure 7 17 Change Ra tes in Buffer 3 Example 7 37 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 228: ...te that the high order bit is set because it is the last parameter the highest value which may be sent is 124 11111100 The lowest rate which can be implemented by the keyboard is 12 Hz values as low as 1 can be transmitted but are translated to 12 Hz The system 11111101 command NOTE module must This code not send 125 is the power up 7 5 6 Special Considerations This section describes consideration...

Page 229: ...d is unlocked are processed as new keys An error code upon unlocking the keyboard indicates a possible loss of keystrokes to the system module The keyboard stops scanning its matrix when its buffer is full However it processes all incoming commands 7 5 6 3 for the routines Reserved internal Code The number 7F hexidecimal is reserved keyboard input and output buffers that handle 7 5 6 4 Test Mode T...

Page 230: ...buffers The volume levels for the keyclick eight step range The default volume keyclick and bell are the third loudest and bell have an levels for the For the LK201 keyboard the CNTRL control key defaults to the no keyclick state 7 5 7 1 Audio decima 1 010 keyboard the unless enabled Bll SHIFT keys Volume Both keyclick and bell volumes are two binary by default The key in position C99 of the CNTL ...

Page 231: ...e type modular connectors plugs into display monitor PN BCC01 Sculptured key array 30 mm 1 16 in above desk top 105 matte textured finish keys 57 keys 18 keys 20 keys firmware and software driven 10 keys 1 9 cm 0 75 in center to center single width keys Less than 0 5 cm 0 020 in Power up self test generates identification upon passing test 5 cm 2 0 in at highest point 53 3 cm 2 1 in 17 1 cm 6 75 i...

Page 232: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 233: ... documents in the introduction to this manual to identify VR241 documents SYSTEM BOX Figure 8 1 LOGIC VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM INTEGRAL COMMUNICATION EIA PRINTER 20 rnA OPTIONAL HOST PORT PORT HOST PORT COMMUNICATIONS MONITOR VR201 OR VR241 MA 0054 84 VT240 Series Terminal System Block Diagram 8 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisant...

Page 234: ...f the cabinet to prevent electromagnetic radiation A folding carrying handle is on the bottom rear of the cabinet The glass front of the monitor the CRT face is specially treated to reduce glare The monitor viewing angle is adjustable between 5 to 25 degrees To adjust the angle the operator pushes a release button on the right side Figure 8 2 This causes a friction lock foot to lower from the bott...

Page 235: ...ASE Figure 8 2 _ CRT FACE CABINET J3 J 1 CONTRAST BRIGHTNESS FOOT FOLDING HANDLE MA 10 500 Monochrome Monitor Exterior View 8 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 236: ... signal consists of two types of information video data refer to section 8 3 1 and sync data refer to section 8 3 2 The monitor module provides the following power to the CRT Anode vol tage Grid 1 vol tage br ightness Grid 2 vol tage cutoff Grid 4 vol tage focus Heater voltage Ca thode vo 1 tag e The control inputs to the CRT refine the electron beam The anode voltage attracts the beam to the face...

Page 237: ...he yoke controls the sweep of the electron beam horizontally across the faceplate each sweep is called a scan line The vertical signal controls the positioning of the beam to a new scan line for vertical positioning 8 4 MONOCHROME MONITOR SYSTEM COMMUNICATION The monochrome monitor connects with both the system box and the keyboard The system box connects to the monitor via Jl a IS pin D type subc...

Page 238: ...Da ta Receive Data Send MA 10 113 Monochrome Monitor System Communications Diagram Description None Video signal ground potential Operational voltage ground potential Operational voltage input None Composite video refer to section 8 3 1 Tied to pins 5 and 6 Serial data line from the keyboard output to the system box via J3 Serial data line from the system box output to the keyboard via J3 8 6 Arti...

Page 239: ...t levels of illumination within the video signal ranging from totally black to maximum brightness Figure 8 5 represents a typical composite video signal and identifies the major terms associated with it This signal used with the monochrome monitor is dc coupled to ground at the monitor module Table 8 3 lists typical signal values Figure 8 6 shows the composite video signal and the sync portion of ...

Page 240: ...west voltage value amplified linearly at the electronics board High limit of display value It equals 100 percent of peak to peak value 1 0 V nominal and is highest voltage value amplified linearly at the electronics board Voltage value which reduces CRT electron beam current below cutoff Voltage level at which sync actions can take place 0 V nominal dc coupled video to ground 2 0 V maximum 2 0 V s...

Page 241: ...V 50 Hz INT 24 5 SCANS lrLJin1 VERTICAL INTERVAL TIME_ n I START OF ODD FIELD H BLANK 11 84 s 50 ns F 12 34 s 50ns 80 COLUMN 132 COLUMN V I H PERIOD 63 56 s 01 NOTES IN NON INTERLACED OPERATION THE EVEN FIELD IS REPEATED CONTIN UOUSLY AND THE ODD FIELD IS NOT USED IN THE INTERLACED OPERATION THE EVEN FIELD ALTERNATES WITH THE ODD FIELD ALL FIELDS CONTAIN 240 DISPLAYED SCANS BLACK 29 V _ 1 1 1 1 f ...

Page 242: ... vertical retrace activity Delay value between start of blanking and start of sync pulse Period of time the actual synchronizing of the vertical deflection circuitry on the electronics board takes place Consists of six EQ pulses six V sync pulses and six more EQ pulses The CRT provides the final video output an electron beam fired at a phosphor coated faceplate Electron beam generation is controll...

Page 243: ...l 8 6 YOKE The yoke is a set of electromagnetic devices mounted on the CRT neck One device is for horizontal deflection of the electron beam the other is for vertical deflection Currents to control the horizontal scan line yokels coil inductance through the width linearity inductor The vertical trace control the vertical processor chip are applied to the inductor and the current comes from The yok...

Page 244: ... function of the position of the beam on the tube 8 7 2 Grid Bias This circuit generates CRT biasing values focus G4 cutoff G2 and brightness Gl These voltages are developed from the flyback transformer Voltages from this transformer are routed to the G4 and G2 circuits There are two resistor networks that each contain potentiometers for adjusting the bias in question R43 for G4 focus or R120 for ...

Page 245: ... horizontal deflection IC also provides the correct timing on its output pulse This allows the current ramp to continue after the damper diode stops conducting The width coil portion of the output stage adjusts the width of the display Two of the RC networks contain potentiometers for adjusting their biasing values R2l1 for hold horizontal and R218 for centering phase A secondary output from the g...

Page 246: ...sts of an input and output stage The video signal is applied to an input push pull transistor network which is part of an encapsulated transistor array The input is provided from R5 the contrast thumbwheel potentiometer The operator can adjust the potentiometer for personal contrast preference The potentiometer Rl19 provides a preamplifier adjustment to preset the range that can be affected by the...

Page 247: ...h the clip lead of the anode discharge tool to the metal frame 3 Hold the tool by its insulated handle Using one hand carefully slide the tip of the tool under the plastic anode cap until it touches the anode Avoid scratching or poking the glass CRT envelope 4 Once discharged remove the tool and clip lead There is also 700 Vdc on the monitor module near the flyback transformer Use caution when per...

Page 248: ...ctor provides the horizontal and vertical deflection currents between the electronics board and the yoke assembly It is a four pin connector Pins one and four are used for vertical deflection pins two and three are used for horizontal deflection 8 7 19 PI This connector mounts on the electronics board that the CRT plugs into Figure 8 8 shows the PI pin out Figure 8 8 VIDEO 12 VDC GROUND RETURN P1 ...

Page 249: ...he logic board SYSTEM BOX Figure 9 1 VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 rnA HOST PORT PORT PORT INTEGRAL OPTIONAL HOST COMMUNICATIONS MONITOR VR201 OR VR2411 MA Q054 84 VT240 Series Terminal System Block Diagram 9 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 250: ...ut and fan components Power supply 1 PS1 DC power input connector Jl 5 V input circuit 12 V input circuits 12 V input circuit DC power Okay P S 1 ACINPUT AND FAN COMPONENTS FROM AC SOURCE LOGIC BOARD 5V INPUT CI RCUIT 12V INPUT CI RCUITS 12V INPUT CIRCUITS DC POWER OK 12V 12VC 12V 5 1V MA 0397 84 Figure 9 2 Power Supply Block Diagram 9 2 Artisan Technology Group Quality Instrumentation Guaranteed ...

Page 251: ...Sl provides the voltage selection switch S2 provides the power on off switch that connects ac input to the PSI via the PSI LN connector a two pin quick disconnect jack F2 provides a 3 amp 250 Vac input line fuse I FAN ASSEMBLY I IB1I I FAN L_ I _ 1 NOTFS 1 S2 SHOWN IN N O 230V f B L1A i 26 INO CONNECTION COMMON PS1 2 Sl SHOWN FOR 115VAC CONFIGURATION 1230VAC HAS NO CONNECTION 115V 2 1 2A 115V Sl I...

Page 252: ...ecification PS 3021383 0 0 The PSI electrical components Figure 9 5 are all located on a single PCB The PSI consist of the following circuits components Jl fan provides the connector for routing 12 VA to the J2 provides the 19 pin connector for routing dc potentials to the system box logic board J3 provides the two pin connector to input ac from the on off switch Jl Pl FAN SHOWN TRANSPARENT LFl F2...

Page 253: ...egulation consists of components responsible for ac input and regulation of isolation inrush current undervo1tage overvo1tage and high voltage transient conditions FROM ON OFF SWITCH 51 v SWITCH PIN CONNECTORS INPUT REGULATION o 230V COMMON 115V CONNECTED TO 51 FOR 115V SELECTION NOT CONNECTED FOR 230V PS1 COMPONENT CARD 5V CROWBAR 1 B 12VA J2 DC Figure 9 5 Power Supply 1 PS1 Block Diagram 9 5 TO ...

Page 254: ... input regulation circuits Figure 9 7 is a circuit schematic of the dc output circuit and Figure 9 8 is a circuit schematic of the 5 1 V crowbar circuits Figure 9 9 shows the layout of the PSl components on the PCB DBl FROM ON OFF SWITCH 52 TMl Vr rrv r 4 __ ur __RN2 __ O L L rrYY _ R3 LTAGE 230V SE LECT WY SWITCH 115V 51 C4 R4 T2 4 TO DC CIRCUITS iL5 1V CROWBAR C8 L3 NOTE WINDING SHOWN IS SECONDA...

Page 255: ...0 27 1 R23 F Zl SCRl 28 r r 18 f R24 22 J T ICl TO 5 1V CROWBAR r C25 T DC Output Circuits FROM T2 R16 1 L5 R17 D16 03 R18 R19 R20 f R21 C29 Ici R22 r l 5 1 V Crowbar Circuit 9 7 130 12VA 12VB 5 1V GROUND 12V MA 0402 84 5 1V OUTPUT R25 GRO LINE UND J R30 R26 R27 MA 0403 84 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 256: ...L2 C6 B01 D Fl 25A 250V D g L O G B I C2 IC3 i R2 c J TMI c J IC4 R3 MA 0404 84 Figure 9 9 PSl Component Layout Table 9 1 lists the component values for the PSl components shows in Figures 9 6 9 7 and 9 9 Table 9 2 provides specification information for the ac voltages Table 9 3 provides the same information for dc voltages Refer to section 9 2 3 a description of Jl on the logic board for a pin ou...

Page 257: ...ectifier Silicon diode Rectifier Schottky diode Bridge rectifier Fuse Regulator Regulator Choke Choke Choke Choke Choke NPN transistor NPN transistor PNP transistor 9 9 Description 0 1 uF 20 250 V 0 22 uF 10 250 V 2200 pF 10 250 V 0 1 uF 10 400 V 100 uF 20 250 V 470 uF 50 10 250 V 1000 pF 20 3 KV Z5P Not used 0 22 uF 10 100 V 1000 uF 100 10 10 V 220 uF 100 10 25 V 100 uF 50 10 25 V 680 uF 100 Y0 1...

Page 258: ...3 5 1 4 W R15 Carbon film 270 5 1 2 W R16 Metal oxide film 220 5 1 W R18 Carbon film 330 5 1 4 W R19 Carbon film 56 5 1 4 W R21 Carbon film 12 K 5 1 4 W R22 Carbon film 470 5 1 4 W R23 220 5 R24 Carbon film 12 5 1 4 W R25 Metal film 2 7 K 1 1 4 W R26 2 1 K 1 R29 Carbon film 680 5 1 4 W R30 Carbon film 68 5 1 4 W SCl CER capacitor 0 01 uF 20 100 V Z5U SCRl Rectifier SCR C122U SRl Carbon film resist...

Page 259: ...25 A peak thermisters cold 120 W max at full rated dc output load of 77 W 0 65 minimum output power to input power ratio Provides minimum of 5 millisecond hold up at 90 Vrms during power outage 150 Vac for 1 second maximum Low energy transient of 300 V peak spike with no more than 0 2 watt seconds of energy per spike High energy transient of 1 KV peak spike with no more than 2 5 wattseconds of ene...

Page 260: ...rm stability Overcurrent Overvo1 tage Nominal output Minimum load Maximum load Ripple and noise Total regulation Long term stability Overcurrent Value 5 1 V 4 A 6 5 A 50 mV peak to peak maximum see note 3 to 5 0 1 1000 hr No damage for any permanent overcurrent averaging 7 8 A or less with peak current of 10 A or less in any 10 second period or for a permanent short circuit 6 9 V maximum with crow...

Page 261: ...veraging 2 8 A or less with peak current of 3 A or less in any 10 second period or for a permanent short circuit short circuit current specified as 1 A maximum 12 V 0 03 A 0 3 A 50 mV peak to peak maximum see note 5 to 5 0 1 1000 hr No damage for any permanent overcurrent averaging 0 5 A or less with peak current of 2 A or less in any 10 second period or for a permanent short circuit short circuit...

Page 262: ...ts from 5 1 V input Figure 9 11 shows the components circuit as well as the various developed by this circuit 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 PART OF PS1 12V 12V GROUND GROUND GROUND GROUND GROUND 12VB 12VA KEY 12VA GROUND 5 1V 5 1V 5 1V OH DL 12V 4 12V 5 6 7 8 9 10 11 12 13 14 PART OF LOGIC BOARD that 5 V make up the 5 V input operating potentials m FOR PRODUCTION TESTING TO 12V INPUT GND...

Page 263: ... C42 O IUF r GB r i c 5 D 16 5 1V 17 18 C12 150UF 15V C9 560PF C1 C2 C7 C8 C19 C27 C14 C203 C207 C211 C219 C221 C231 C23B C239 C241 C244 C246 C253 C25B C259 C264 C221 19 Figure 9 11 t4 22UF I 5 V Input Ci rcui t TO KEY BOARD CONNECTOR J61 TO EIA PORT IIF TO PRINTER PORT IIF 12V 12V 12V 12V TO INTEGRAL MODEM CONNECTOR J51 r r L TODCPOWEROK 12BV JC10 1 __ 560PF GND _ J1 PINS Figure 9 12 12VC TO MONI...

Page 264: ...indication of dc input to the logic board Figure 9 14 shows that 5 V 12 V and 12 V potentials are applied as inputs to the dc power okay circuit When all three inputs are present Q2 is properly biased and 02 a light emitting diode LED lights 08 IN4004 1 rlIIIt 12V J1 PINS Figure 9 13 5V E6 3 4 7K 12A R38 220 L __ 5 1V 01 IN5231B 5 1V 5 1 2W C24 22UF C240 560PF MA 0408 84 12 V Input Circuit R43 3 3...

Page 265: ...a host computer by using the terminal keyboard instead of a telephone set The modem has three operating modes accessible through the VT2413 terminal data mode talk mode and dialer mode SYSTEM BOX VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 mA HOST PORT PORT PORT OPTIONAL HOST COMMUNICATIONS MONITOR VR201 OR VR2411 MA Q054 84 Figure 10 1 VT240 Series Terminal Block Diagram ...

Page 266: ...llowing features Direct connect telephone line interface Automatic answer Automatic originate dialing Test modes Speed control Keyboard control 10 1 2 Functional Description The integral modem connects to the system communication logic on the system logic board This modem is a full duplex asynchronous binary serial data communications device It is used to transmit and receive data over a two wire ...

Page 267: ...ace TLI The modem connects to the system logic board via a 3 pin stacK connector Figure 1 2 The telephone line and the telephone set connect to the TLI standard miniature telephone jacKs STANDOFFS Figure 10 2 Physical Description 10 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 268: ...alk data relay circuit Figure 10 4 connects the telephone line to either the handset or the modem The position of the talk data switch on the VT240 keyboard determines whether the handset or modem is connected When the talk data switch is pressed the TALK DATA signal is inverted and passed through the stack connector to the modem module When the TALK DATA signal is low the relay circuit is in talk...

Page 269: ...MOD MODEM 614 4 KHz CLOCK ffiTERCLK w f 0 Ol U Z l Ol w is J N N r r r f fl r c c fl 0 I Ol fl U 0 f G Ol f Ol Ol Ol 0 u u fl c Ol Ol f U U c f l J 0 Z f I STACK CONNECTOR TERM Figure 10 3 Block Diagram RI HOOK RELAY LINE INTERFACE TELEPHONE r l J RING RING LINE t It rY 0 0 I Tc IP__ ____ _T Ic P_ l TALK TALKIDATALr r r DA OHO OHM RING SWITCH TELEPHONE TIP HOOK SW HANDSET DETECT MA 0415 84 Figure ...

Page 270: ...ng leads from the talk data relay to the protective circuit and is used to pulse dial the telephone system during the automatic dialing mode The signal OHD is passed from the terminal through the stack connector and operates the Hook Relay The signal OH is inverted becomes OHM and is returned to the terminal through the stack connector During the pulsed dialing sequence data from the terminal keyb...

Page 271: ...e following elements Figure 10 5 Hybrid amplifier High low filter Filter circuit Hybrid Amplifier The hybrid ampifier full duplex transmit channels AUDIO H 0 IC data AUDIO cL JA I COUPLER ANALOG OHD TEST UJ 0 0 x 0 N 0 fJ 0 u 0 z f0 X a X Coupler cut through relay Mix circuit Limiter amplifier threshhold detector E2 splits the signal AUDIO H into AUD XMIT and receive data FILTER A MA 0416 84 CCT R...

Page 272: ...z range The receive data signal FILTER A has a carrier frequency in the 700 1700 Hz range The filter input switch routes the XMOD signal into the high bandpass filter and outputs the signal XMIT A to the HYBRID amp The FILTER A signal is routed to the low bandpass filter and output as the signal REC Loopback Test When the modem is in the loopback test mode Figure 10 8 the data signal XMOD is passe...

Page 273: ...10 7 CCT HYBRID AMPLIFIER Figure 10 8 FILTER SWITCH X MOD ANS MODE MA 0418 84 Originate Mode MA 0419 84 Answer Mode FILTER SWITCH XMIT A X MOD ANS MODE MIX MA 0420 84 Test Mode 10 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 274: ...10 9 consists of the components Yl and E43 Yl generates a square wave clock signal with a frequency of 4 9152 MHz which is then divided into the following four subfrequency signals CLOCK A CLOCK B FILTER CLOCK 614 4 kHz 10 2 9 Modem Control LSI Circuit The modem control LSI circuit Figure 10 10 consists of two large scale integration LSI chips that perform the following tasks ClK MODEM 614 4 KHz C...

Page 275: ... The circuit also detects the presence of a valid received data carrier and inputs the signal carrier detect CD back to the terminal The circuit generates the control signals CTS and DSR These signals are sent to the terminal The input control signals DTR 9 10 SELECT and CH are received from the terminal These signals inform the modem control LSI circuit of the bit count of the transmitted data by...

Page 276: ...e when the circuit voltage is more positive than 2 V with respect to signal ground and in the spacing condition when the voltage on the circuit is more negative than 2 V with respect to signal ground The signal is considered off when it is more positive than 0 8 V with respect to signal ground HJ 3 2 State Ma rki ng Spacing Off Vol tage 2 V 2 V 8 V Interface Signals The following sections describe...

Page 277: ...eserved Vol tage Coupler cut through Switch hook Off hook Test analog loop Remote digital loop Test mode indicator Da te term ready Clear to send Carrier detect Vol tage Source Active Level Term Modem Modem Modem Term Term Term Term Term Modem Term Modem Modem Term Modem Modem Modem Term Term Modem Term Modem Modem Term Low Low space Low 1299 bps Low space High 1299 bps Low CCT Low OH relay Low 19...

Page 278: ...c power 10 3 2 6 Carrier Detect CD Carrier detector on indicates that a data carrier is being received and has been received for at least 155 milliseconds This circuit differentiates a good data carrier from message circuit noise or out of band signals This circuit turns off if the received data is clamped to the marking state 10 3 2 7 Speed Indication CI This circuit is on when the modem is in th...

Page 279: ...de or data mode to the modern 10 3 2 12 Data Available DA This signal is generated by the terminal to request a data transmission path cut through For pulse dialing the terminal disables the DA signal after detecting a dial tone before generating the dial pulses corresponding to the called number 10 3 2 13 Off Hook Drive OH D The terminal generates this signal to drive the off hook relay When the ...

Page 280: ...oopback Test RDL This interface signal causes the local 2l2A modem to put the remote 212A modem into a data loop Data from the terminal is then transmitted from the local modem to the remote modem and back again thus checking the local and remote modems and the line 10 3 2 20 Test Mode Indicate Test IND The modem generates this signal whenever it is in the test mode 10 16 Artisan Technology Group ...

Page 281: ...0 kg 4 5 1bs terminals Height 29 2 em 11 5 in Width 34 9 em 13 75 in Depth 31 1 em 12 25 in Weight 6 4 kg 14 1b Adjustable Tilt 5 _25 He i g h t 3 2 4 em 1 2 75 in Width 38 0 em 15 in Depth 42 1 em 17 0 in Weight 16 6 kg 36 6 1b Temperature 10 40 C 50 104 F Relative Humidity 10 90 Maximum Wet Bulb 28 C 82 F Minimum Dew Point 2 C 36 F Maximum Altitude 2 4 km 8000 ft Temperature _40 66 C 140 151 F R...

Page 282: ...ers 7 X 9 dot matrix in 10 X 10 cell for 80 columns 5 X 9 dot matrix in 6 X 10 cell for 132 columns 3 35 mm X 2 0 mm for 80 columns 3 35 mm X 1 3 mm for 132 columns 202 mm X 115 mm 8 X 5 in ASCII DEC Supplemental Special Graghics UK loadable 80 or 132 column font Control characters using control representation mode 80 column font only Reverse video underline bold blinking maximum of 100 characters...

Page 283: ... finish keys home row key height is 30mm 1 18 in above desk top 1 27 cm 0 5 in square 1 9 cm 0 75 in center to center single width keys 18 keys 36 keys firmware and software dr i ven 4 LED indicators hold lock wait and compose Keyclick provides audible feedback for each keystroke Bell sounds when BEL character is received when approaching right margin and for compose errors Multiple Bell sounds on...

Page 284: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 285: ...r OEM supplied character ROM NO SCROLL key 25 pin 50 60 Hz Display in English only Performs power up self test 7 pixels with 2 pixels between characters Off line mode disconnects modem B 1 VT240 Not programmable Down line loadable character set HOLD SCREEN key 9 pin 60 Hz only Display in three languages and display does not affect software Does not perform power up self test 5 pixels with 1 pixel ...

Page 286: ...baud rate Selectable passive or active 20 rnA ESC 6 c B 2 VT240 Full duplex mode only and does not affect softwa re Optional transmit speed limitation of 150 characters per second Passive 20 rnA only CSI 62 1 2 3 4 6 7 8 c primary CSI 2 Pv Po c secondary Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 287: ...phics Scales X and Y directions independently when mapping Uses integral divisions to map screen addressing range to physical pixels Ignores digits after a decimal point in screen addressing parameters and coordinates Supports screen scaling C l VT240 800 X 240 displayed pixels Pixels outside defined screen addressing range but inside visible screen are not drawable clipped No off screen memory fo...

Page 288: ...r is slashed C 2 VT240 Images moved off screen are lost Scrolls image on 16 pixel boundaries horizontally and single pixel boundaries vertically When image is moved origin remains fixed at point defined by screen addressing command Shading to horizontal and vertical baseline Does not use italic attribute when drawing shaded area with character fill 32 entries Images that rely on on position stack ...

Page 289: ...ntire screen Text can overlay graphics in same display region Erases text and graphics separately Changes only presentation of graphics image ESC 12 Pvt00 Pf Pvc C 3 VT240 Provides only for optional external monitor on which same image is displayed as on standard monitor No Text and graphics must scroll together ReGIS commands used to display graphics images appear on line 24 of screen Text drawn ...

Page 290: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 291: ...ANSMIT CHARACTER 01 1y STOP BITS PER TRANSMIT CHARACTER 11 2 STOP BITS PER TRANSMIT CHARACTER a a ODD PARITY GENERATION CHECK EVEN PARITY GENERATION CHECK PARITY DISABLED PARITY ENABLED BIT 2 3 00 5 BITS PER CHARACTER BIT 0 1 Figure D l 10 6 BITS PER CHARACTER 01 7 BITS PER CHARACTER 11 8 BITS PER CHARACTER 00 SYNC MODE 10 BAUD RATE FACTOR OF 1X 01 BAUD RATE FACTOR OF 16X 11 BAUD RATE FACTOR OF 64...

Page 292: ...BIT 2 BIT 1 BIT 0 Figure 0 2 o o o o o o o BIT VALUES DISABLE SEARCH FOR SYNC CHARACTERS SEARCH FOR SYNC NO EFFECT IN ASYNC INACTIVE INTE RNAL RESET NOT USED INACTIVE RESET ERROR FLAGS NORMAL OPERATION FORCE TxD CONSTANT LOW RECEIVE ENABLE DISABLED RECEIVE ENABLE ENABLED DTR DISABLED DTR FORCED LOW GENERATING LPBK EN L TRANSMIT ENABLE DISABLED TRANSMIT ENABLE ENABLED MA 017g 84 8251A USART Command...

Page 293: ...ET NO STOP CHARACTER DETECTED NO OVERRUN ERROR OE FLAG OE FLAG SET CPU FAILED TO READ Rx CHARACTER BEFORE NEW Rx CHARACTER NO PARITY ERROR PE FLAG PE FLAG SET PARITY ERROR SENSED NOT READY FOR Tx DATA TxD READY FOR TxD GENERATES KYBD INTR2 L NO Rx DATA RxD PRESENT RxD PRESENT GENERATES KYBD INTR1 L TxD BUFFER FULL TxD BUFFER EMPTY MA 0181 84 8251A USART Status Register D 3 Artisan Technology Group...

Page 294: ...BIT 5 0 CHARACTER ERROR MODE BLOCK ERROR MODE BIT 3 4 00 WITH PARITY 01 FORCE PARITY 10 NO PARITY 11 SPECIAL MODE BIT 2 0 EVEN PARITY ODD PARITY BIT 0 1 00 5 BITS PER CHARACTER 01 6 BITS PER CHARACTER 10 7 BITS PER CHARACTER 11 8 BITS PER CHARACTER 01 00 I BITS PER CHAR1CTER ROAD HI MA_0182_84 Figure D 4 2681 DUART Mode Register MR1 Channel A and B D 4 1 Artisan Technology Group Quality Instrument...

Page 295: ...0 0 688 BIT STOP CHARACTER 0011 0 750 BIT STOP CHARACTER 0100 0 813 BIT STOP CHARACTER 0101 0 875 BIT STOP CHARACTER 0110 0 938 BIT STOP CHARACTER 0111 1 000 BIT STOP CHARACTER 1000 1 563 BIT STOP CHARACTER 1001 1 625 BIT STOP CHARACTER 1010 1 688 BIT STOP CHARACTER 1011 1 750 BIT STOP CHARACTER 1100 1 813 BIT STOP CHARACTER 1101 1 875 BIT STOP CHARACTER 1110 1 938 BIT STOP CHARACTER 1111 2 000 BI...

Page 296: ...RROR BIT VALUES NO BREAK DETECTED RECEIVE BREAK DETECTED NO ERROR FRAMING ERROR NO ERROR PARITY ERROR NO ERROR OVERRUN ERROR Tx NOT EMPTY Tx HOLDING AND SHIFT REGISTERS EMPTY Tx HOLDING REGISTER FULL Tx HOLDING REGISTER EMPTY Rx FI FO NOT FU LL Rx FIFO FULL NO Rx DATA WAITING Rx DATA IN FIFO MA 0234 84 2681 SR DUART Status Register Channel A and B D 6 Artisan Technology Group Quality Instrumentati...

Page 297: ...0 9600 1100 38 4K 19 2K 1101 TIMER TIMER 1110 IP4 16X RxCA IP4 16X RxCA 1110 IP6 16X RxCBI IP6 16X RxCB 1110 IP3 16X TxCA IP3 16X TxCA 1110 IP5 16X TxCB IP5 16X TxCB 1111 IP4 1 X RxCA IP4 1 X RxCAI 1111 IP6 1 X RxCB IP6 1 X RxCB 1111 IP3 1 XITxCA IP3 1XITxCA 1111 IP5 1 X TxCB IP5 1 XITxCB NOTES 1 RxC AND TxC ARE ALWAYS 16X EXCEPT FOR 1111 CONDITION 2 SET SELECTION MADE BY ACR BIT 7 Figure D 7 MA 0...

Page 298: ...TS BIT 2 0 DISABLE Tx ENABLE Tx BIT 1 0 NO COMMAND TERMINATE Rx IMMEDIATELY BIT 0 0 DISABLE Rx ENABLE Rx MA 0236 84 Figure D 8 2681 DUART Command Register CR Channel A and B RDRA ADDRESS 172014 RD RDRB ADDRESS 172056 RD TDRA ADDRESS 172016 WR TDRB ADDRESS 172060 WR 07 06 05 04 03 02 01 00 RDA7H RDAOH BIT 0 7 Figure D 9 BIT VALUES DATA RECEIVED FROM HOST RDRA DATA RECEIVED FROM PRINTER RDRB DATA TO...

Page 299: ... CHANGE OF STATE DETECTED AT IPl CHANGE OF STATE DETECTED AT IPl NO CHANGE OF STATE DETECTED AT IPO CHANGE OF STATE DETECTED AT IPO CURRENT STATE OF IP3 CURRENT STATE OF IP2 CURRENT STATE OF IPl CURRENT STATE OF IPO MA 0238 84 2681 OUART Input Change Reg i ster ICR 04 03 02 01 00 IP4 IP3 IP2 IPl IPO RDAO H BIT VALUES CURRENT STATE OF IP6 MOD2 SI L CURRENT STATE OF IP5 HOST DSR L CURRENT STATE OF I...

Page 300: ...ER MODE TxCB AT 1X CLOCK OF CHANNEL B Tx COUNTER MODE CRYSTAL OR EXTERNAL CLOCK CLK DIVIDED BY 16 TIMER MODE EXTERNAL IIP2 SOURCE TIMER MODE EXTERNAL lP2 SOURCE DIVIDED BY 16 TIMER MODE CRYSTAL OR EXTERNAL ICLK SOURCE TIMER MODE CRYSTAL OR EXTERNAL ICLK SOURCE DIVIDED BY 16 NO INTERRUPT ON CHANGE OF STATE SET ISR BIT 7 ON DETECT OF CHANGE OF STATE AT IP2 NO INTERRUPT ON CHANGE OF STATE SET ISR BIT...

Page 301: ...ESS 172026 WR 07 06 05 04 03 02 01 00 INPUT DELTA RxRDY TxRDY COUNTER DELTA RxRDY TxRDY PORT BREAK FFULL B READY BREAK FFUL CHANGE B B A A A RDA7 H ROAD H BIT VALUES BIT 7 0 INTERRUPT DISABLED INPUT PORT CHANGE OF STATE INTERRUPT ENABLED BIT 6 0 INTERRUPT DISABLED CHANGE IN BREAK STATE INTERRUPT ENABLED CH B BIT 5 0 INTERRUPT DISABLED RxRDY FFULL INTERRUPT ENABLED CH B BIT 4 0 INTERRUPT DISABLED T...

Page 302: ...IGURE OP4 AS COMPLIMENT OF Rx INTERRUPT RxRDY FFULL A COMPLIMENT OP3 FOR MOD SPD SEL L FALSE OUTPUT COMPLIMENT OP3 FOR MOD SPD SEL L TRUE OUTPUT COMPLIMENT OP2 FOR HOST DTR L FALSE OUTPUT COMPLIMENT OP2 FOR HOST DTR L TRUE OUTPUT COMPLIMENT OP1 FOR PRTR DTR L FALSE OUTPUT COMPLIMENT OP1 FOR PRTR DTR L TRUE OUTPUT NOT USED CONFIGURE OPO AS COMPLIMENT OF ENABLED RTSA MA 0244 84 Figure D 16 2681 DUAR...

Page 303: ...O DATA AVAILABLE DATA AVAILABLE BIT 4 0 DOMESTIC MODEM TYPE BELL 103 EUROPEAN MODEM TYPE V 21 BIT 3 0 10 BITS PER CHARACTER 9 BITS PER CHARACTER BIT 2 0 TALK MODE DATA MODE BIT 0 1 00 EIA HOST PORT 01 NO CONNECTION 10 20 mA PORT 11 INTEGRAL MODEM NOTE BIT 4 IS OVERRIDDEN BY MCWR BIT50N 1 MA 0245 84 Figure D 17 Comm Modem Control Comm Control Write CCWR and Read Registers CCRD D 13 Artisan Technolo...

Page 304: ...ALUES BIT 7 0 DIAL TONE DETECTED NO DIAL TONE DETECT BIT 6 0 OUTPUT OF MCWR BIT 6 SELECTS ORIGINATE MODE OUTPUT OF MCWR BIT 6 SELECTS ANSWER MODE BIT 5 0 OUTPUT OF MCWR BIT 5 SELECTS BELL 103 OR V 21 OUTPUT OF MCWR BIT 5 SELECTS BELL 212A BIT 4 0 COUPLER CUT THROUGH CONDITION NO COUPLER CUT THROUGH CONDITION BIT 3 0 INTEGRAL MODEM IN TEST MODE INTEGRAL MODEM IN NORMAL MODE BIT 2 0 SWITCH HOOK COND...

Page 305: ...GOC Status Register ADDRESS 174600 WR CPU ADDRESS COH WR CP 07 06 05 04 03 02 01 00 ERA SVP SGDC SLU SVEC EVOM SM1 SMO VDB7H 4 VDBOH BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 0 1 00 01 10 11 BIT VALUES ERASE SCREEN ENABLED DISABLE SCREEN ERASE SELECT CHARACTER BUFFER PATTERN FOR LOGIC UNIT SELECT VECTOR PATTERN REGISTER PATTERN FOR LOGIC UNIT SELECT OTHER THAN READ BACK MODE SELECT READ ...

Page 306: ...RESS BOH WR CP 07 06 05 04 03 02 01 00 M1 MO IF1 IFO IB1 IBO SP PS VDB7 H 4 VDBO H BIT VALUES BIT 6 7 00 REPLACE WRITING 10 OVERLAY WRITING 01 NOT USED 11 COMPLIMENT WRITING BIT 5 0 1 FOREGROUND INTENSITY VALUE PLANE 1 BIT 4 0 1 FOREGROUND INTENSITY VALUE PLANE 0 BIT 3 0 1 BACKGROUND INTENSITY VALUE PLANE 1 BIT 2 0 1 BACKGROUND INTENSITY VALUE PLANE 1 BIT 1 0 2 PLANE WRITING SINGLE PLANE WRITING B...

Page 307: ...03 02 01 00 WE 7 LI WEO L LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 x x x x x x x X M1 MO IF1 IFO IB1 IBO SP PS M1 1 H I I JH IF1 H IB1 H MO H IFO H IBO H PS H NOTES 1 GDC COMMANDS USE CURS COMMAND TO SET WORD ADDRESS AND PLANE SELECT USE FIG COMMAND TO SET DIRECTION AND BYTE COUNT USE WDAT COMMAND TO EXECUTE WORD BYTE READ THEN READ THROUGH FIFO 2 X INDICATES DON T CARE MA 0173 B4 Figure E l Mo...

Page 308: ...LATCH 07 06 05 04 03 02 01 00 IWETL IWEOl LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 ISET APPROPRIATELY IPS IMl H IIFl H IIBl H ISP H IMO H liFO H IIBO H IPS H NOTES 1 GDC COMMANDS USE CURS COMMAND FOR SETTING WORD ADDRESS USE FIG AND WDAT COMMAND FOR GENERATING WRITE ADDRESS USE A16 FOR lOW HIGH BYTE CONTROL 2 X INDICATES DON T CARE Figure E 2 Mode 1 Text Mode Programming Values E 2 MA 0172 84 A...

Page 309: ...SEL SD H NOT USED WRITE MASK LATCH 07 06 05 04 03 02 01 00 X X X X X X X X 4 _ WEOL WE T LI LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 SET APPROPRIATELY PS M1 H IF1 H IB1 H SP H MO H IFO H IBO H PS H NOTES 1 PROGRAM GDC FOR PATTERN OF ALL 1 s REPLACEMENT MODE 2 X INDICATES DON T CARE MA 0175 84 Figure E 3 Mode 2 Vector Mode Programming Values E 3 Artisan Technology Group Quality Instrumentation G...

Page 310: ... 04 03 02 01 00 a a a a a a a a WE T LI WEO LI LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 a 1 a a a a a a M11 Mal IF11 IFOI IB11 IBOI SPI PSI M HI I I JHI IF1 HI IB1 HI MO HI IFO HI IBO HI PS HI NOTES 1 GDC COMMANDS USE CURS COMMAND TO SET START OF SOURCE ADDRESS USE FIG COMMAND TO SET WORD COUNT USE WDAT COMMAND TO EXECUTE 2 X INDICATES DON T CARE MA 0177 84 Figure E 4 Mode 3 OMA Scroll Mode Pro...

Page 311: ...06 05 04 03 02 01 a a a 0 a a a WE T L LOGIC UNIT REGISTER 07 a M1 M H 06 05 04 03 02 01 DESI ED 0 x X INTENSITY a MO IF1 IFO IB1 I IBO SP IJ H I JH IB1 H MO H IFO H IBO H NOTES 1 SET VECTOR PATTERN REGISTER TO ALL a s 2 REGISTER a VALUES IN EFFECT FOR ONE FRAME TIME 3 X INDICATES DON T CARE 00 a WEO L 00 x PS PS H MA 0174 84 Figure E 5 Mode 4 Screen Erase Mode Programming Values E 5 Artisan Techn...

Page 312: ...5 04 03 02 01 00 a a 0 a a 0 0 0 WE T L WEO L LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 a a X X DESIRED a X INTENSITY M1 MO IIF1 liFO IIB1 I IBO SP PS M H I IIB1 H JH lF1 H MO H IFO H IBO H PS H NOTES 1 USE FIG COMMAND TO SET WORD COUNT AND DIRECTION 2 SET VECTOR PATIERN TO ALL O s 3 X INDICATES DON T CARE MA 018Q 84 Figure E 6 Mode 5 Word Line Erase Mode Programming Values E 6 Artisan Technolog...

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