Environmental Data
Table 3–17 (Cont.)
System DC Power Requirements (Using 21068A at
100 MHz)
Nominal
Input
Typical Load
Current
Maximum Load
Current
Required
Regulation
-12 V
—
23 mA
±10%
3.2.2
Power Sequencing
Power sequencing of +3.3 V for the Alpha processor by the power supply
is not required. The +3.3 V supply is derived from +5 V and sequenced by
an onboard circuit. The +3.3 V power connector provides power only to the
PCI slots.
3.2.3
POWER GOOD Signal
The POWER GOOD (assert HIGH) signal to the MLB is required to ensure
that the logic to the system comes up and goes down in a defined state.
On power up, the AXPpci 33 power supply asserts the POWER GOOD
signal 100–500 ms after the dc power is within the operating range. On
power down, the power supply must furnish regulated power levels for
a period greater than 1 ms after the POWER GOOD signal negates (see
Figure 3–1). The POWER GOOD signal input is TTL compatible.
Tables 3–18 and 3–19 define the recommended electrical characteristics
for the power supply and POWER GOOD signal, which is fed into a 74F00
type gate. No required relationship exists b5 V valid levels and
the turn on or turn off of the ±12 V, -5 V, or +3.3 V supplies.
Figure 3–1
POWER GOOD Timing Diagram
POWER GOOD
100 500 ms
+5 VOLTS
1 ms
Power Up
Power Down
MR-6409-AI
3–10
Summary of Contents for AXPpci 33
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