Digital Equipment DMO9AL, Instruction Manual

Page 1: ...INSTRUCTION MANUAL DMOSA ADAPTER MULTIPLEXER DIGITAL EQUIPMENT CORPORATION MAYNARD MASSACHUSETTS...

Page 2: ...DMDSA ADAPTER MULTIPLEXER INSTRUCTION MANUAL DEC 09 19AA D DIGITAL EQUIPMENT CORPORATION MAYNARD MASSACHUSETTS...

Page 3: ...pyright 1968 by Digital Equipment Corporation The following are registered trademarks of Digital Equipment Corporation Maynard Massachusetts DEC FLIP CHIP DIGITAL ii PDP FOCAL COMPUTER LAB October 196...

Page 4: ...Detailed 4 4 2 1 Power Turn On 4 4 2 2 Internal Control Pulse Train 4 4 2 3 Single Fast Input Cycle 5 4 2 4 Single Slow Output Cycle 6 4 2 5 Double Back to Back Fast Output Cycles 7 5 Acceptance Test...

Page 5: ...CONTENTS Cant TABLES Reference Documents Single Fast Input Cycle Signal Flow Single Slow Output Cycle Signal Flow Double Back to Back Fast Output Cycles Signal Flow Module Complement Engineering Draw...

Page 6: ...ance of the option The level of discussion assumes that the user is fami liar with the basic PDP 9 1 1 Related Documentation The DEC documents listed in Table 1 1 contain material which supplements in...

Page 7: ...3 Physica I The DM09A consists entirely of modules which are housed by two DEC standard 1943 mount ing panels thus requiring 10 1 2 in of mounting space Placement of these panels is given in Sec tion...

Page 8: ...10 CD D DM09 A 11 Title Memory Interface Interface Cabling DM09 Memory Cabling DMA Inter Memory 4 PRINCIPLES OF OPERATION 4 1 Basic Description Interface between the DM09A and the basic PDP 9 memory I...

Page 9: ...synchronized to the PDP 9 or in which a data transfer takes place With multiple transfers synchronization is established during the previous data transfer When reading the logic descriptions the user...

Page 10: ...mory read write cycle During this time the I O device break request flag is set providing the DM09A with a CH 0 BK RQ level Referring to Table 4 1 and the referenced engineering drawings internal cont...

Page 11: ...esult of AM GRANT or AM GRAND SMlTD The flip flops designated AMEMA 03 and AMEMA 04 are used with PDP 9 systems containing extended memory banks Inverter inputs are CH 0 ADDR BIT 03 and SET AO l for A...

Page 12: ...AM RQ and AM RQ NEG AM RQ signals the PDP 9 that a DMA cycle is de sired the computer responds with AM SYNC l B The A PHASE pulse of SYNCING 1 sets SET AO and generates CLR SYNC This clears SYNC O SE...

Page 13: ...O l AM GRANT From PDP 9 CH 0 ADDR ACC A PHASE SET AO l SET DO l IN DEV 0 CONT l CH 0 ADDR ACC IN SET DO l DEVICE 0 DEV 0 CONT l SET DO l CH 0 RQ IN SET AO 0 A PHASE SYNC 0 0 SET DO l CH 0 ADDR ACC CH...

Page 14: ...T CLR CLR SYNC SYNC 0 1 SYNC 0 0 CLR SYNC SYNC 0 1 SET 00 1 D PHASE SET DO EN AM GRANT From PDP 9 CH 0 ADDR ACC A PHASE SET AO l SET 00 1 IN DEV 0 CONT l CH 0 ADDR ACC IN SET DO 1 SET AO O A PHASE SYN...

Page 15: ...rom PDP 9 MC 2 1 DATA XFER 1 A PHASE CH 0 ADDR ACC A PHASE SET AO l SET 00 1 SYNCING 2 IN DM 2 1 CH 0 ADDR ACC CH 0 ADDR ACC IN DM02 l DEV 0 CONT l SET DO 1 CH 0 ADDR ACC IN DM 2 1 AM STROBE From PDP...

Page 16: ...O Margin rack A 3 DM09A O Margin rack B Minimum margin specifications for rack A and rack B are listed below Margin 10V 15V 6V I 6V 4V 4V 6 MAINTENANCE 6 1 General The general maintenance procedures...

Page 17: ...AWINGS Table 7 1 lists the DEC engineering drawings associated with the D A09A option Drawing Number DM 2 1 DM 2 2 DM 3 1 DM 3 2 DM 4 1 DM 4 2 DM 5 DM S l DM S 2 Table 7 1 Engineering Drawings Title D...

Page 18: ...ADDR Ace IN 1 D CH I ADDR Ace CH 2 ADDR Ace CH DATA Ace CH I Rq IN wl1Jr is CI9 58 A2 I SET D2 1 Ace eN 2 RQIN_ SLOW CYCLE 0 I eLR W rj5 C 19 CH 2 F ST C LR CH OAT A RDY HJ CH I DATA RD I IN CH 2 D TA...

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Page 20: ...ASE B 4 I M RQ AM RQ NE AMI SAL A D 4 3 CHQRQIN DEV CONTROL I DEV SET 0 i J I CH 1 RQ IN CONTROL I SE T D 1 I A2d LOflD lMEMA CH Z RQ IN DEV 2 CONTROL I SET D2 I U PK CLR I A 3 2 W 5 A2 I D 1M DEVICE...

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Page 22: ...0 DEVI CH 2 DATA BIT DEV2 M C NOTE loon tw lOt TERM INATORS TO GROUND MUST BE PUT ON SA00 THRU SA 17 8 SA 12 SAl CH 0 DATA BIT 12 DEV 0 CH I DATA BIT 12 DEV I CH 2 DATA BIT 12 7 6 5 3 2 D c M loon B M...

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Page 24: ...M 16 BIT 17 CWI AOO BIT 17 CH 2 ADDP BI T 17 6 6 LAM 0 5 LAM 06 CH 0ADoR BIT 1216 CH IAOoR BIT 06 CH 2 AOoP BIT 1216 C M LAMI7 c 5 4 LAM 67 LAM I2IB CH 0 AODP CH 0AoOR CHrllAODR BIT07 BIT 08 BIT 0 9 C...

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Page 26: ...S T V SA i J QlI 02 03 4 15 06 07 SA 18 4 SA 09 1 1 II 12 13 14 15 16 SA 17 USED FOR TERMINATION ONLY NOT A CABLE IOPTIONAL W031 013 Wy 33 A04 5 AM i JC I I JI 1 J2 03 04 05 1 J6 07 AM 08 I AM C J9 I...

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Page 28: ...1 E 1 FI I 1 1 11 K Flc f JI M 7 I 1 P I Li 5 41 Ml 7 401 I Nt I I L ___ J OPTIONAL CLAMPED LOADS 5 4 eH q r DDR SII cjJ9 Irb II 12 I l t IS CO CH C J I DDR CIT 7 CH 2 DF BIT 09 1 Iq II 2 j 14 IS I D...

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Page 30: ...WN CYCLE f CONTROl V f A CLR I IN 0 SLW A18L 8Z11V f f B2B11 J V IL62 D PHASE eye f EN J B21L iAMEMA MEMA SLOWf V LAM LAM LAM LAII LAII LAM LAM LAM LAM AODR DEV ICE OEV ICE rGAR CYCLE OEV I CLR A17H_...

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Page 32: ...9fl TO MEMORY SYNCX I _ r SYNc x_o 1 r _ _________________________ _______________________________ I I I I t I I I 200 NS r 200NS 400 NS i MAX r MAX ________________________________M_A_X ____ L _____...

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Page 34: ...EMORY CH X FI7ST CLU R Ff eofVI DfYlO 91i TO DEV X 7 6 5 4 SINGLE SLOW OUTPUT CYCLE 0 SYNC tNG 8 y U 120N5 U 120 NS __________ r SET D X I SET II X i A PHIlSE U 320 NS u ___________ 1 SLOW yc LI SHD x...

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Page 36: ...E RII l 01 1 000 D9fv MFD RIO 100 10 7 Q1 012 011 F DI6 Rig 1 000 RI8 100 10 _ C7 r IO MMFO R20 6 800 DI9 H 1 l CIO 3V 022 H R23 6 800 020 R25 lrn 01 1 000 B MFD R24 100 10 t D24 II 014 3 5V IOV _ h D...

Page 37: ...l r _1 _ _ _ _ _ I C GNO 6 1 Eo _____ o II 1 7 Il00 1 K I 015 D 884 Lo t o Q2 DEC 3639 010 0 884 012 0 884 II Dli 0 884 8 013 0 882 T R7 II 115 000 7 1500 15 1 82l I 018 I 0 882 1 017 0 882 018 0 882...

Page 38: ...8 ql 09 R3 J H RI R2 07 R5 12 000 12 000 3 000 10 10 UNLESS OTHERWISE INDICATED TRANSISTORS ARE DEC 3639C RESISTORS ARE 15 000 RESISTORS ARE 1 4W 15 CAPACITORS ARE MMFO DIODES ARE 0 664 Orl R6 3 000 r...

Page 39: ...TORS AR E DEC 3639 C 1 P L 013 UO B CS S203 0 1 Triple Flip Flop 0 100pa 023 10 000 100 000 035 10 000 5 4 5 03 04 05 06 7 DEC h 2894 28 DEC R24 R25 2894 28 62 47 B J62 47 0 1 2 j3 M T 18 iio B 2 O 66...

Page 40: ...E INDICATED RESISTORS ARE 1 4W 10 De 011 DE I DE 4 ARE DEC NO 330 2I1E 6 R 8 010 012 Dl4 S T U V 011 013 B CS WOOS O 1 Clamped Loads R7 7 500 5 B CS W300 0 1 35 Delay Line 0111 Rill 3 000 II 02 01 MFO...

Page 41: ...1 500 0662 CII 0682 CIO c ______ I ______ 015 59 0 _____ 1 ______ 051 at 0662 MFO 0662 MFO 014 030 0662 0662 013 029 0662 0662 41 012 41 028 RI2 7 500 0662 0882 011 027 0862 D25 0882 RI4 1 500 RI5 RI8...

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