Specifications
dimtel
dimtel
Table 5: Data acquisition controls
Parameter
Definition
Recording memory selection
FPGA internal blockRAM or external
SRAM
Measurement trigger
Internal or external
External trigger arming
Single or after every beam data read-
out
Recorded growth length
Adjustable in units of 4 samples, up to
full memory length
Hold-off before recording
In units of 4 samples, 0 to 2
32
−
1
Recording downsampling
1 to 32
Table 6: Monitoring and diagnostics
Parameter
Definition
Clock status
Feedback channel status
FIR saturation
Acquisition state machine status
Trigger arming bit
Voltages
FPGA core supply, 3.3 V, 12 V bulk
Temperatures
Fast ADC,
ambient,
two
emitter coupled logic (ECL)
devices,
IOC CPU
Fan speeds
Chassis and CPU IOC
Analog inputs
8 slow ADC channels
Digital inputs
32 general-purpose inputs/outputs
38 of 58