dimtel
dimtel
5.3
Display Panels
5.3.5
Timing Panel
Figure 9: Timing panel
This window provides controls for system timing.
ADC delay
High-speed ADC clock delay in picoseconds. This adjustment
is independent of the back-end timing (DAC delay) and has a range
from 0 to
T
rf
−
1 ps. Rounding to 10 ps adjustment step size is handled
automatically.
DAC delay
High-speed DAC clock delay in picoseconds. This adjustment
is independent of the front-end timing (ADC delay) and has a range
from 0 to
T
rf
−
1 ps. Rounding to 10 ps adjustment step size is handled
automatically.
OUTPUT DELAY
High-speed DAC output delay in units of RF periods.
FIDUCIAL DELAY
Input fiducial delay in steps of two bunches. Use to
place bunch 1 signal in channel 1 of the data acquisition. For example,
if bunch 1 signal is seen in acquisition channel 3, increment this field
by 1. Fiducial delay of one bunch can be achieved by adjusting
FID
SIGNAL OFFSET
by one RF period.
DCM RESET
Pushbutton for resetting feedback processing DCM (DCM1)
and data acquisition DCM (DCM2). Push this button if
DCM unlocked
indicators are red and the RF clock is present at the iGp-5120F front
panel. On rare occasions due to intermittent RF clock loss DCM might
need to be reset even though lock indicators are green.
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