9.1
Registers
dimtel
dimtel
Table 9 – continued from previous page
Address
Bits
Definition
0x000018
15:0
FIR coefficient 12, set 0
0x000019
15:0
FIR coefficient 12, set 1
0x00001a
15:0
FIR coefficient 13, set 0
0x00001b
15:0
FIR coefficient 13, set 1
0x00001c
15:0
FIR coefficient 14, set 0
0x00001d
15:0
FIR coefficient 14, set 1
0x00001e
15:0
FIR coefficient 15, set 0
0x00001f
15:0
FIR coefficient 15, set 1
9.1.2
Gateware Config Register
Gateware config register (
0x107
) provides information about the unit’s func-
tionality, gateware revision, harmonic number, and processing demultiplex-
ing.
Table 10: FPGA registers: control and status
Address
Bits
Definition
0x000100
Main control register
0
Data acquisition trigger
1
Reserved
2
Coefficient set select, 0 - set 0, 1 - set 1
3
FIR channel disable, 1 - disabled
6:4
Shift gain, 0 through 7
7
DCM reset
8
Grow/damp enable
9
Trigger select, 1 - external
10
External trigger arming, arms on rising edge
11
SRAM interface select, 0 - local bus, 1 - ADC
12
ADC test pattern generator enable
Continued on next page
1
Gateware revision 1.2 and higher
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