dimtel
dimtel
2.2
System Overview
iGp-5120F signal processor is designed for the bunch-by-bunch feedback
and diagnostics in lepton storage rings. Functionally iGp-5120F implements
a baseband bunch-by-bunch processing channel configured for 5120 bunches.
Each bunch is processed in a 8-tap finite impulse response (FIR) filter before
being sent to the one-turn delay and, from there, to the high-speed digital-
to-analog converter (DAC).
A block diagram of the iGp-5120F system is shown in Figure 1. The main
signal processing chain consists of a high-speed analog-to-digital converter
(ADC), a field programmable gate array (FPGA), and a high-speed DAC
and is driven by the radio frequency (RF) clock. In addition to performing
real-time control computations, the FPGA interfaces to a number of on-
board devices, such as high-speed data acquisition memory (static random
access memory (SRAM)), low-speed analog and digital input/output (I/O),
as well as temperature and supply voltage monitors. In turn, the FPGA
uses an internal universal serial bus (USB) connection to communicate to
an embedded input-output controller (IOC) computer housed in the same
chassis. The IOC runs the Linux operating system and is connected to the
overall control system via the Ethernet.
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