DRS WJ-8611 Installation, Operation And Maintenance Manual Download

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WJ-8611 DIGITAL VHF/UHF RECEIVER

CIRCUIT DESCRIPTIONS

5-9

band-limited to 200 kHz and its amplitude is limited to a maximum level
of 0.2 V peak-to-peak when loaded into 50 ohms.

There are four synthesizer circuits contained in the 2nd LO/ 2nd Converter
PC Assembly (A3A2). They are the 10 MHz reference generator, the 100
MHz synthesizer, the 2nd LO synthesizer, and the 3rd LO synthesizer.

The reference generator contained in the 2nd LO/2nd Converter PC
Assembly (A3A2) uses a 10 MHz temperature compensated voltage
controlled crystal oscillator TCVCXO as its tuned circuit. It produces a
stable 10 MHz signal that is supplied to each of the synthesizers in the
receiver. It also supplies its 10 MHz reference to a 100 MHz synthesizer
to produce the 100 MHz reference for the circuitry in the Digital Control
PC Assembly (A2). The reference generator is designed for free running
operation, or, an externally supplied 1, 2, 5, or 10 MHz reference may be
applied at rear panel connector J2. Application of a reference signal at a
level of at least 0 dBm triggers an auto-sensing circuit to notify the Digital
Control PC Assembly (A2) that an external signal has been applied. It sets
the REF SENSE line (A3A2P3, pin 33) to logic “0” when a signal is
present, or to logic “1” when no signal is applied. Applying an external
reference signal causes a reference synthesizer to be activated, and an
attempt is made to lock the TCVCXO to the external signal. The Digital
Control PC Assembly (A2) sends tuning data to attempt to lock the
reference synthesizer to each of the allowable frequencies (1, 2, 5, 10
MHz) and monitors the REF LOCK line (A3A2P3, pin 29) for a locked
condition (logic ”1”). If no lock is obtained, or if the external reference
signal is removed, the Digital Control PC Assembly (A2) disables the
reference synthesizer and switches the TCVCXO to internal free-running
operation. In the internal reference mode the TCVCXO frequency is set
by a fixed DC bias voltage. Potentiometer R325 permits fine-tuning of the
TCVCXO for a 10.0000 MHz output when in the Internal Reference mode.
The output of the reference generator is buffered and routed to the other
synthesizers in the receiver for use as a common time-base. Two of the
outputs (TP30 and TP31) are used as the reference for the 2nd LO
synthesizer. The output at TP32 provides the output for the 3rd LO
synthesizer, and the TP33 output is the reference for the 100 MHz
synthesizer. The final 10 MHz output (TP34) is directed out terminal E4
and is used by the 1st LO/ 1st Converter PC Assembly (A3A1) as its time-
base.

The 100 MHz synthesizer, phase-locked to the 10 MHz reference signal,
provides its output to the Digital Control PC Assembly (A2) via connector
A3A2P2. It consists of a 100 MHz VCO, a divide-by-ten feedback path,
and a phase detector. One input to the phase detector is a 10 MHz
reference from the reference generator. The second phase detector input is
the divided down sample from the VCO. When the oscillator is operating
at the correct frequency, the divided-down VCO sample is equal to 10
MHz. Any deviation from the required output frequency is reflected by a
frequency difference between the VCO sample and the 10 MHz reference.
The phase detector then attempts to correct the VCO frequency by

DRS WJ-8611, Installation, Operation And Maintenance Manual

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