DRS WJ-8611 Installation, Operation And Maintenance Manual Download

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WJ-8611 DIGITAL VHF/UHF RECEIVER

CIRCUIT DESCRIPTIONS

5-17

anti-alias filter in the RF Tuner Assembly (A3), and the signal amplitude is
limited to a maximum of from 6 to 10 dB below the full-scale range of the
A/D converter used for digitization. Upon entering the assembly, the
signal is routed through a 20 dB amplifier prior to digitization. Test point
TP77 provides a point to verify the incoming analog signal after
amplification. The peak-to-peak amplitude of the signal at this point is
approximately ten times the peak-to-peak level at the J2 input connector
(approximately 20 V peak-to-peak), with a DC level of +2.05V. The
analog signal is applied to a 12-bit analog to digital converter where the
signal is sampled at a 1 MHz rate and is converted into the stream of 12-bit
digital words. In addition to the analog signal, the input to the A/D
converter circuit contains DC bias circuit, and a low level noise signal
from a filtered noise source. The amplitude of the noise input is factory set
by R96 to provide for the best A/D converter performance. The DC bias is
set to the center of the A/D converter’s input range for the best peak-to-
peak signal handling performance. The bias is set by R447 to +2.05V at
TP77. The parallel data representing the IF signal is interfaced with the
Digital Signal Processing section by the Flexible Logic integrated circuits
in the Control Processor section. The signal is converted to serial data that
can be handled by the DSP circuits.

The Digital Signal Processing (DSP) section consists of a series of
Programmable Serial I/O Digital Filters, a Numerically Controlled
Oscillator, and two 32-bit DSP Processors (DSP A and DSP B). These
processing components interface with the Control Processor section and
other support circuits through two programmable Flexible Logic integrated
circuits.

The Programmable filters, along with Numerically Controlled Oscillator,
aid in the signal processing by performing fine tuning of the receiver to a
10 Hz resolution by performing IF and video filtering. The outputs are the
complex I (In phase) and Q (Quadrature) signals that are provided to the
DSP Processors for further processing. The DSP algorithms associated
with manual and automatic gain control, automatic frequency control,
signal strength calculations, noise blanking, and demodulation of the signal
intelligence is handled by the two 32-bit DSP processors. Upon
completion of the signal demodulation, the digital data is converted to a
stream of parallel data bytes that are applied to the Analog Reconstruction
and Output section through the interface provided by the Flexible Logic
circuits.

An additional output from the Flexible Logic circuits provides I and Q IF
data from the Programmable Serial I/O Digital Filters to the rear panel
Digital IF Interface (J14) for output to external digital signal processing
equipment. This output is the post filtered IF signal in the form of
complex I and Q data. The output consists of I and Q data words, each 16
bits in length, that are transferred out at a 10 MHz rate. Each 16-bit data
word is accompanied by a data strobe that marks the start of each word for
synchronization of the data with the receiving equipment. Finally, an I/Q
qualifier provides an indication of the type data being output (Logic “1”=I
data; Logic “0”= Q data). The differential outputs from the interface are:

DRS WJ-8611, Installation, Operation And Maintenance Manual

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