T5L_ASIC Development Guide
- 34
-
www.dwin-global.com
DWIN Technology
Professional,
Creditable,
S
uccessful
3.9.2 Interrupt Priority
The interrupt priority of T5L OS CPU is handled according to the following rules.
(1) Twelve interrupts are divided into six groups with two interrupts in each group. The priority in the
same group is fixed. For example, the priority of interrupt 0 is higher than that of UART3, as shown in
the table below.
Grouping
IP0
correspondence
IP1 correspondence
Interrupt correspondence
High priority
Low priority
G0
.0
.0
External interrupt 0
UART3 interrupt
G1
.1
.1
T0 timer interrupt
CAN communication interrupt
G2
.2
.2
External interrupt 1
UART4 send interrupt
G3
.3
.3
T1 timer interrupt
UART4 receive interrupt
G4
.4
.4
UART2 interrupt
UART5 send interrupt
G5
.5
.5
T2 timer interrupt
UART5 receive interrupt
(2) There are four levels of priority among the six groups, which can be configured by the
corresponding bits of IP0 and IP1 according to the table below.
Inter group priority
IP1 counterpart
IP0 counterpart
3(highest)
1
1
2
1
0
1
0
1
0(lowest)
0
0
For example, if you want to set the G2 group's T2 timer interrupt and UART5 receive interrupt priority
to the highest, you can set 1P1=0x20, 1P0=0x20.
(3) If the configurations have the same priority (IP1 = 0x00 IP0 = 0x00), the G0 group has the highest
priority and the G5 group has the lowest priority. The interrupt priority weights with the same
configuration are as follows:
Weight
11
10
9
8
7
6
5
4
3
2
1
0
Priority
Maximum
Minimum
Interrupt
EX0
UART3 ET0 CAN EX1 UART4-TX ET1 UART4-RX UART2 UART5-TX ET2 UART5-RX
(4) High priority interrupts can be embedded in low priority interrupts (i.e. interrupts with small
weights can be interrupted by interrupts with large weights), and at most four levels can be
embedded.
