Embedded Solutions
Page 8
Other Options
Dynamic Engineering offers multiple versions of the cPCIxPMC design.
cPCI2PMC is a passive implementation. The cPCI connections on the
cPCI2PMC are longer, and can limit the number of cards or adapters on a
particular bus segment. The passive design has “0” delay between the primary
PCI bus and the PMC. The VIO and bus speed definitions are common to the
primary PCI bus and PMC. This design is versatile with PCI 32, PCI 64, rear IO
versions and a slot zero configuration.
cPCIBPMC3U32 is bridged, isolating the PMC from the cPCI bus. cPCI
connections are specification compliant on cPCIBPMC3U32. cPCIBPMC3U32
can be used in multiple positions on the same PCI bus segment. The bridged
design has pipeline delays between the primary and PMC buses. The bridged
design has independent VIO definitions between the PMC and the primary bus.
This design (cPCIBPMC6U) is the 6U 2 PMC position variant.
All optional signals can be isolated or added with resistors located to create short
stubs when the signals are not in use.
