EMR-5000
IM02602012E
Name
Description
Logic.LE10.Timer Out
Signal: Timer Output
Logic.LE10.Out
Signal: Latched Output (Q)
Logic.LE10.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE11.Gate Out
Signal: Output of the logic gate
Logic.LE11.Timer Out
Signal: Timer Output
Logic.LE11.Out
Signal: Latched Output (Q)
Logic.LE11.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE12.Gate Out
Signal: Output of the logic gate
Logic.LE12.Timer Out
Signal: Timer Output
Logic.LE12.Out
Signal: Latched Output (Q)
Logic.LE12.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE13.Gate Out
Signal: Output of the logic gate
Logic.LE13.Timer Out
Signal: Timer Output
Logic.LE13.Out
Signal: Latched Output (Q)
Logic.LE13.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE14.Gate Out
Signal: Output of the logic gate
Logic.LE14.Timer Out
Signal: Timer Output
Logic.LE14.Out
Signal: Latched Output (Q)
Logic.LE14.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE15.Gate Out
Signal: Output of the logic gate
Logic.LE15.Timer Out
Signal: Timer Output
Logic.LE15.Out
Signal: Latched Output (Q)
Logic.LE15.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE16.Gate Out
Signal: Output of the logic gate
Logic.LE16.Timer Out
Signal: Timer Output
Logic.LE16.Out
Signal: Latched Output (Q)
Logic.LE16.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE17.Gate Out
Signal: Output of the logic gate
Logic.LE17.Timer Out
Signal: Timer Output
Logic.LE17.Out
Signal: Latched Output (Q)
Logic.LE17.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE18.Gate Out
Signal: Output of the logic gate
Logic.LE18.Timer Out
Signal: Timer Output
Logic.LE18.Out
Signal: Latched Output (Q)
Logic.LE18.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE19.Gate Out
Signal: Output of the logic gate
Logic.LE19.Timer Out
Signal: Timer Output
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