EMR-5000
IM02602012E
Name
Description
Logic.LE15.Out
Signal: Latched Output (Q)
Logic.LE15.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE16.Gate Out
Signal: Output of the logic gate
Logic.LE16.Timer Out
Signal: Timer Output
Logic.LE16.Out
Signal: Latched Output (Q)
Logic.LE16.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE17.Gate Out
Signal: Output of the logic gate
Logic.LE17.Timer Out
Signal: Timer Output
Logic.LE17.Out
Signal: Latched Output (Q)
Logic.LE17.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE18.Gate Out
Signal: Output of the logic gate
Logic.LE18.Timer Out
Signal: Timer Output
Logic.LE18.Out
Signal: Latched Output (Q)
Logic.LE18.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE19.Gate Out
Signal: Output of the logic gate
Logic.LE19.Timer Out
Signal: Timer Output
Logic.LE19.Out
Signal: Latched Output (Q)
Logic.LE19.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE20.Gate Out
Signal: Output of the logic gate
Logic.LE20.Timer Out
Signal: Timer Output
Logic.LE20.Out
Signal: Latched Output (Q)
Logic.LE20.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE21.Gate Out
Signal: Output of the logic gate
Logic.LE21.Timer Out
Signal: Timer Output
Logic.LE21.Out
Signal: Latched Output (Q)
Logic.LE21.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE22.Gate Out
Signal: Output of the logic gate
Logic.LE22.Timer Out
Signal: Timer Output
Logic.LE22.Out
Signal: Latched Output (Q)
Logic.LE22.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE23.Gate Out
Signal: Output of the logic gate
Logic.LE23.Timer Out
Signal: Timer Output
Logic.LE23.Out
Signal: Latched Output (Q)
Logic.LE23.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE24.Gate Out
Signal: Output of the logic gate
Logic.LE24.Timer Out
Signal: Timer Output
Logic.LE24.Out
Signal: Latched Output (Q)
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