EMR-5000
IM02602012E
Name
Description
Logic.LE2.Gate Out
Signal: Output of the logic gate
Logic.LE2.Timer Out
Signal: Timer Output
Logic.LE2.Out
Signal: Latched Output (Q)
Logic.LE2.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate Out
Signal: Output of the logic gate
Logic.LE3.Timer Out
Signal: Timer Output
Logic.LE3.Out
Signal: Latched Output (Q)
Logic.LE3.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE4.Gate Out
Signal: Output of the logic gate
Logic.LE4.Timer Out
Signal: Timer Output
Logic.LE4.Out
Signal: Latched Output (Q)
Logic.LE4.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE5.Gate Out
Signal: Output of the logic gate
Logic.LE5.Timer Out
Signal: Timer Output
Logic.LE5.Out
Signal: Latched Output (Q)
Logic.LE5.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE6.Gate Out
Signal: Output of the logic gate
Logic.LE6.Timer Out
Signal: Timer Output
Logic.LE6.Out
Signal: Latched Output (Q)
Logic.LE6.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE7.Gate Out
Signal: Output of the logic gate
Logic.LE7.Timer Out
Signal: Timer Output
Logic.LE7.Out
Signal: Latched Output (Q)
Logic.LE7.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE8.Gate Out
Signal: Output of the logic gate
Logic.LE8.Timer Out
Signal: Timer Output
Logic.LE8.Out
Signal: Latched Output (Q)
Logic.LE8.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE9.Gate Out
Signal: Output of the logic gate
Logic.LE9.Timer Out
Signal: Timer Output
Logic.LE9.Out
Signal: Latched Output (Q)
Logic.LE9.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE10.Gate Out
Signal: Output of the logic gate
Logic.LE10.Timer Out
Signal: Timer Output
Logic.LE10.Out
Signal: Latched Output (Q)
Logic.LE10.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE11.Gate Out
Signal: Output of the logic gate
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