32 Interface module XN-322-2SSI
32.4 Memory layout
274
XN300 slice modules
06/16 MN050002 EN
www.eaton.com
4101
1
State and Configuration Register
Channel 1
Bit 0.1
SSI Shift Register Frequency
00 = 125 kHz
01 = 250 kHz
10 = 500 kHz
11 = 1 MHz
Bit 2
0: Binary Data
1: Gray Code Decoding
Bit 3
SSI busy (1= busy) (read only)
Bit 4
Reserved
Bit 5
Error Clear (1 = clear error) (write)
Bit 6
Start with Sync (1= enable)
Bit 7
Continuous Sensor Read (1= enable)
4102
1
Configuration Register Channel 2
(Default 0x20)
Bit 0 … 5
SSI Shift Register ; Length: 1-32 Bit
Bit
5 4 3 2 1 0
0 0 0 0 0 0 reserved
0 0 0 0 1 1 1-bit register
0 0 0 0 1 0 2-bit register
…
0 1 1 1 1 1 31-bit register
1 0 0 0 0 0 32-bit register
1 0 0 0 0 1 reserved
… reserved
1 1 1 1 1 1 reserved
Bit 6
Read mode:
0: Single Read
1: Double Read
Bit 7
reserved
4103
1
State and Configuration Register
Channel 2
Bit 0.1
SSI Shift Register Frequency
00 = 125 kHz
01 = 250 kHz
10 = 500 kHz
11 = 1 MHz
Bit 2
0: Binary Data
1: Gray Code Decoding
Bit 3
SSI busy (1= busy) (read only)
Bit 4
Reserved
Bit 5
Error Clear (1 = clear error) (write)
Bit 6
Start with Sync (1= enable)
Bit 7
Continuous Sensor Read (1= enable)
2100 3100
1
Channel Control /
Channel Control Status
Starts read cycle
Bit 0
Start Read Channel 1
Bit 1
Start Read Channel 2
Bit 2…7
reserved
CAN Object
Index
Size
(byte)
Description
Bit
Summary of Contents for XN300
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