9 Appendix
9.1 Data image of the technology modules
XI/ON: XNE-GWBR-2ETH-MB
10/2011 MN05002008Z-EN
www.eaton.com
159
STS_OFLW
Status upper count limit
Set if the counter goes above the upper count limit.
This bit must be reset by the RES_STS control bit.
STS_CMP2
Status comparator 2
This status bit indicates a comparison result for comparator 2 if:
– The output DO2 is released with CTRL_DO2 = 1.
and
– a comparison is run via MODE_DO2 = 01, 10 or 11.
Otherwise STS_CMP2 simply indicates that the output is or was
set. STS_CMP2 is also set if DO2 SET_DO2 = 1 when the output
is not released.
This bit must be reset by the RES_STS control bit.
STS_CMP1
Status comparator 1
This status bit indicates a comparison result for comparator 1 if:
– The output DO1 is released with CTRL_DO1 = 1.
and
– a comparison is run via MODE_DO1 = 01, 10 or 11.
Otherwise STS_CMP1 simply indicates that the output is or was
set. It must be acknowledged with RES_STS (process output). The
bit is reset immediately if acknowledgement takes place when the
output is still set. STS_CMP1 is also set if DO1 SET_DO1 = 1 when
the output is not released.
This bit must be reset by the RES_STS control bit.
STS_SYN
Status synchronization
After synchronization is successfully completed the STS_SYN
status bit is set.
This bit must be reset by the RES_STS control bit.
Table 76:
Process input
data - counter
mode of
XN-1CNT-
24VDC
Bits
Value, meaning
